/* Date Stamp: 8/23/2014 */

#ifndef IIO_DFX_GLOBAL_h
#define IIO_DFX_GLOBAL_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_DFX_GLOBAL_DEV 6                                                       */
/* IIO_DFX_GLOBAL_FUN 7                                                       */

/* VID_IIO_DFX_GLOBAL_REG supported on:                                       */
/*       IVT_EP (0x20037000)                                                  */
/*       IVT_EX (0x20037000)                                                  */
/*       HSX (0x20037000)                                                     */
/*       BDX (0x20037000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_DFX_GLOBAL_REG 0x12012000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_DFX_GLOBAL_REG supported on:                                       */
/*       IVT_EP (0x20037002)                                                  */
/*       IVT_EX (0x20037002)                                                  */
/*       HSX (0x20037002)                                                     */
/*       BDX (0x20037002)                                                     */
/* Register default value on IVT_EP:    0x0E17                                */
/* Register default value on IVT_EX:    0x0E17                                */
/* Register default value on HSX:       0x2F17                                */
/* Register default value on BDX:       0x6F17                                */
#define DID_IIO_DFX_GLOBAL_REG 0x12012002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100010111 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel QPI
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x20037004)                                                  */
/*       IVT_EX (0x20037004)                                                  */
/*       HSX (0x20037004)                                                     */
/*       BDX (0x20037004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_DFX_GLOBAL_REG 0x12012004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RO, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RO, default = 1'b0 
       1
     */
    UINT16 sce : 1;
    /* sce - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 mwie : 1;
    /* mwie - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 perre : 1;
    /* perre - Bits[6:6], RW, default = 1'b0 
       1
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RW, default = 1'b0 
       1
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RO, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x20037006)                                                  */
/*       IVT_EX (0x20037006)                                                  */
/*       HSX (0x20037006)                                                     */
/*       BDX (0x20037006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_DFX_GLOBAL_REG 0x12012006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxstat : 1;
    /* intxstat - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fb2b : 1;
    /* fb2b - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 mdpe : 1;
    /* mdpe - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 devselt : 2;
    /* devselt - Bits[10:9], RO, default = 2'b00 
       1
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RO, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RO, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_DFX_GLOBAL_REG supported on:                                       */
/*       IVT_EP (0x10037008)                                                  */
/*       IVT_EX (0x10037008)                                                  */
/*       HSX (0x10037008)                                                     */
/*       BDX (0x10037008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_DFX_GLOBAL_REG 0x12011008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x10037009)                                                  */
/*       IVT_EX (0x10037009)                                                  */
/*       HSX (0x10037009)                                                     */
/*       BDX (0x10037009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_DFX_GLOBAL_REG 0x12011009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x2003700A)                                                  */
/*       IVT_EX (0x2003700A)                                                  */
/*       HSX (0x2003700A)                                                     */
/*       BDX (0x2003700A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_DFX_GLOBAL_REG 0x1201200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x1003700C)                                                  */
/*       IVT_EX (0x1003700C)                                                  */
/*       HSX (0x1003700C)                                                     */
/*       BDX (0x1003700C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_DFX_GLOBAL_REG 0x1201100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CLSR_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* PLAT_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x1003700D)                                                  */
/*       IVT_EX (0x1003700D)                                                  */
/*       HSX (0x1003700D)                                                     */
/*       BDX (0x1003700D)                                                     */
/* Register default value:              0x00                                  */
#define PLAT_IIO_DFX_GLOBAL_REG 0x1201100D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x00d
 */
typedef union {
  struct {
    UINT8 primary_latency_timer : 8;
    /* primary_latency_timer - Bits[7:0], RO, default = 8'b00000000 
       Not applicable to PCI-Express. Hardwired to 00h.
     */
  } Bits;
  UINT8 Data;
} PLAT_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_DFX_GLOBAL_REG supported on:                                       */
/*       IVT_EP (0x1003700E)                                                  */
/*       IVT_EX (0x1003700E)                                                  */
/*       HSX (0x1003700E)                                                     */
/*       BDX (0x1003700E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_DFX_GLOBAL_REG 0x1201100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* BIST_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x1003700F)                                                  */
/*       IVT_EX (0x1003700F)                                                  */
/*       HSX (0x1003700F)                                                     */
/*       BDX (0x1003700F)                                                     */
/* Register default value:              0x00                                  */
#define BIST_IIO_DFX_GLOBAL_REG 0x1201100F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x00f
 */
typedef union {
  struct {
    UINT8 bist_tests : 8;
    /* bist_tests - Bits[7:0], RO, default = 8'b00000000 
       Not supported. Hardwired to 00h
     */
  } Bits;
  UINT8 Data;
} BIST_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x2003702C)                                                  */
/*       IVT_EX (0x2003702C)                                                  */
/*       HSX (0x2003702C)                                                     */
/*       BDX (0x2003702C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIO_DFX_GLOBAL_REG 0x1201202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b1000000010000110 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* SDID_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x2003702E)                                                  */
/*       IVT_EX (0x2003702E)                                                  */
/*       HSX (0x2003702E)                                                     */
/*       BDX (0x2003702E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_DFX_GLOBAL_REG 0x1201202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x10037034)                                                  */
/*       IVT_EX (0x10037034)                                                  */
/*       HSX (0x10037034)                                                     */
/*       BDX (0x10037034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_DFX_GLOBAL_REG 0x12011034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* INTL_IIO_DFX_GLOBAL_REG supported on:                                      */
/*       IVT_EP (0x1003703C)                                                  */
/*       IVT_EX (0x1003703C)                                                  */
/*       HSX (0x1003703C)                                                     */
/*       BDX (0x1003703C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_DFX_GLOBAL_REG 0x1201103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x1003703D)                                                  */
/*       IVT_EX (0x1003703D)                                                  */
/*       HSX (0x1003703D)                                                     */
/*       BDX (0x1003703D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_DFX_GLOBAL_REG 0x1201103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* MINGNT_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x1003703E)                                                  */
/*       IVT_EX (0x1003703E)                                                  */
/*       HSX (0x1003703E)                                                     */
/*       BDX (0x1003703E)                                                     */
/* Register default value:              0x00                                  */
#define MINGNT_IIO_DFX_GLOBAL_REG 0x1201103E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x03e
 */
typedef union {
  struct {
    UINT8 mgv : 8;
    /* mgv - Bits[7:0], RO, default = 8'b00000000 
       The Device does not burst as a PCI compliant master.
     */
  } Bits;
  UINT8 Data;
} MINGNT_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* MAXLAT_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x1003703F)                                                  */
/*       IVT_EX (0x1003703F)                                                  */
/*       HSX (0x1003703F)                                                     */
/*       BDX (0x1003703F)                                                     */
/* Register default value:              0x00                                  */
#define MAXLAT_IIO_DFX_GLOBAL_REG 0x1201103F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x03f
 */
typedef union {
  struct {
    UINT8 mlv : 8;
    /* mlv - Bits[7:0], RO, default = 8'b00000000 
       The Device has no specific requirements for how often it needs to access the PCI 
       bus. 
     */
  } Bits;
  UINT8 Data;
} MAXLAT_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x40037040)                                                  */
/*       IVT_EX (0x40037040)                                                  */
/*       HSX (0x40037040)                                                     */
/*       BDX (0x40037040)                                                     */
/* Register default value:              0x00920010                            */
#define PXPCAP_IIO_DFX_GLOBAL_REG 0x12014040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x040
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b00000000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0010 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0 
       N/A for integrated endpoints
     */
    UINT32 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[29:25], RO, default = 5'b00000 
       N/A for this device
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* DEVCAP_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x40037044)                                                  */
/*       IVT_EX (0x40037044)                                                  */
/*       HSX (0x40037044)                                                     */
/*       BDX (0x40037044)                                                     */
/* Register default value:              0x00008000                            */
#define DEVCAP_IIO_DFX_GLOBAL_REG 0x12014044
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x044
 */
typedef union {
  struct {
    UINT32 max_payload_size_supported : 3;
    /* max_payload_size_supported - Bits[2:0], RO, default = 3'b000  */
    UINT32 phantom_functions_supported : 2;
    /* phantom_functions_supported - Bits[4:3], RO, default = 2'b00  */
    UINT32 extended_tag_field_supported : 1;
    /* extended_tag_field_supported - Bits[5:5], RO, default = 1'b0  */
    UINT32 endpoint_l0s_acceptable_latency : 3;
    /* endpoint_l0s_acceptable_latency - Bits[8:6], RO, default = 3'b000  */
    UINT32 endpoint_l1_acceptable_latency : 3;
    /* endpoint_l1_acceptable_latency - Bits[11:9], RO, default = 3'b000  */
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[12:12], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[13:13], RO, default = 1'b0  */
    UINT32 power_indicator_present_on_device : 1;
    /* power_indicator_present_on_device - Bits[14:14], RO, default = 1'b0  */
    UINT32 role_based_error_reporting : 1;
    /* role_based_error_reporting - Bits[15:15], RO, default = 1'b1  */
    UINT32 rsvd_16 : 2;
    /* rsvd_16 - Bits[17:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 captured_slot_power_limit_value : 8;
    /* captured_slot_power_limit_value - Bits[25:18], RO, default = 8'b00000000  */
    UINT32 captured_slot_power_limit_scale : 2;
    /* captured_slot_power_limit_scale - Bits[27:26], RO, default = 2'b00  */
    UINT32 rsvd_28 : 4;
    /* rsvd_28 - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* DEVCON_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x20037048)                                                  */
/*       IVT_EX (0x20037048)                                                  */
/*       HSX (0x20037048)                                                     */
/*       BDX (0x20037048)                                                     */
/* Register default value:              0x0000                                */
#define DEVCON_IIO_DFX_GLOBAL_REG 0x12012048
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * The PCI Express Device Control register controls PCI Express specific 
 * capabilities parameters associated with the device. 
 */
typedef union {
  struct {
    UINT16 correctable_error_reporting_enable : 1;
    /* correctable_error_reporting_enable - Bits[0:0], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 non_fatal_error_reporting_enable : 1;
    /* non_fatal_error_reporting_enable - Bits[1:1], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 fatal_error_reporting_enable : 1;
    /* fatal_error_reporting_enable - Bits[2:2], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 unsupported_request_reporting_enable : 1;
    /* unsupported_request_reporting_enable - Bits[3:3], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 enable_relaxed_ordering : 1;
    /* enable_relaxed_ordering - Bits[4:4], RO, default = 1'b0 
       For most parts, writes from CB DMA are relaxed ordered, except for DMA 
       completion writes. But the fact that CB DMA writes are relaxed ordered is not 
       very useful except when the writes are also non-snooped. If the writes are 
       snooped, relaxed ordering does not provide any particular advantage based on IIO 
       uArch. But when writes are non-snooped, relaxed ordering is required to get good 
       BW and this bit is expected to be set. If this bit is clear, NS writes will get 
       very poor performance. 
     */
    UINT16 max_payload_size : 3;
    /* max_payload_size - Bits[7:5], RO, default = 3'b000 
       N/A for CB DMA
     */
    UINT16 extended_tag_field_enable : 1;
    /* extended_tag_field_enable - Bits[8:8], RO, default = 1'b0  */
    UINT16 phantom_functions_enable : 1;
    /* phantom_functions_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to CB DMA since it never uses phantom functions as a requester.
     */
    UINT16 auxiliary_power_management_enable : 1;
    /* auxiliary_power_management_enable - Bits[10:10], RO, default = 1'b0 
       Not applicable to CB DMA
     */
    UINT16 enable_no_snoop : 1;
    /* enable_no_snoop - Bits[11:11], RO, default = 1'b0 
       For CB DMA, when this bit is clear, all DMA transactions must be snooped. When 
       set, DMA transactions to main memory can utilize No Snoop optimization under the 
       guidance of the device driver. 
     */
    UINT16 max_read_request_size : 3;
    /* max_read_request_size - Bits[14:12], RO, default = 3'b000 
       N/A to CB DMA since it does not issue tx on PCIE
     */
    UINT16 rsvd : 1;
    /* rsvd - Bits[15:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVCON_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* DEVSTS_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x2003704A)                                                  */
/*       IVT_EX (0x2003704A)                                                  */
/*       HSX (0x2003704A)                                                     */
/*       BDX (0x2003704A)                                                     */
/* Register default value:              0x0000                                */
#define DEVSTS_IIO_DFX_GLOBAL_REG 0x1201204A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x04a
 */
typedef union {
  struct {
    UINT16 correctable_error_detected : 1;
    /* correctable_error_detected - Bits[0:0], RO, default = 1'b0  */
    UINT16 non_fatal_error_detected : 1;
    /* non_fatal_error_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 fatal_error_detected : 1;
    /* fatal_error_detected - Bits[2:2], RO, default = 1'b0  */
    UINT16 unsupported_request_detected : 1;
    /* unsupported_request_detected - Bits[3:3], RO, default = 1'b0  */
    UINT16 aux_power_detected : 1;
    /* aux_power_detected - Bits[4:4], RO, default = 1'b0  */
    UINT16 transactions_pending : 1;
    /* transactions_pending - Bits[5:5], RO, default = 1'b0  */
    UINT16 rsvd : 10;
    /* rsvd - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVSTS_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* LNKCAP_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x4003704C)                                                  */
/*       IVT_EX (0x4003704C)                                                  */
/*       HSX (0x4003704C)                                                     */
/*       BDX (0x4003704C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP_IIO_DFX_GLOBAL_REG 0x1201404C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x04c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* LNKSTS_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x20037052)                                                  */
/*       IVT_EX (0x20037052)                                                  */
/*       HSX (0x20037052)                                                     */
/*       BDX (0x20037052)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS_IIO_DFX_GLOBAL_REG 0x12012052
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x052
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* LNKCAP2_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x4003706C)                                                  */
/*       IVT_EX (0x4003706C)                                                  */
/*       HSX (0x4003706C)                                                     */
/*       BDX (0x4003706C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP2_IIO_DFX_GLOBAL_REG 0x1201406C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x06c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* LNKCON2_OLD_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x20037070)                                                  */
/*       IVT_EX (0x20037070)                                                  */
/*       HSX (0x20037070)                                                     */
/*       BDX (0x20037070)                                                     */
/* Register default value:              0x0000                                */
#define LNKCON2_OLD_IIO_DFX_GLOBAL_REG 0x12012070
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x070
 */
typedef union {
  struct {
    UINT16 active_state_link_pm_control : 2;
    /* active_state_link_pm_control - Bits[1:0], RO, default = 2'b00  */
    UINT16 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 read_completion_boundary : 1;
    /* read_completion_boundary - Bits[3:3], RO, default = 1'b0  */
    UINT16 link_disable : 1;
    /* link_disable - Bits[4:4], RO, default = 1'b0  */
    UINT16 retrain_link : 1;
    /* retrain_link - Bits[5:5], RO, default = 1'b0  */
    UINT16 common_clock_configuration : 1;
    /* common_clock_configuration - Bits[6:6], RO, default = 1'b0  */
    UINT16 extended_synch : 1;
    /* extended_synch - Bits[7:7], RO, default = 1'b0  */
    UINT16 enable_clock_power_management_na : 1;
    /* enable_clock_power_management_na - Bits[8:8], RO, default = 1'b0  */
    UINT16 hardware_autonomous_width_disable_ioh : 1;
    /* hardware_autonomous_width_disable_ioh - Bits[9:9], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_interrupt_enable : 1;
    /* link_bandwidth_management_interrupt_enable - Bits[10:10], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_interrupt_enable : 1;
    /* link_autonomous_bandwidth_interrupt_enable - Bits[11:11], RO, default = 1'b0  */
    UINT16 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} LNKCON2_OLD_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* LNKSTS2_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x20037072)                                                  */
/*       IVT_EX (0x20037072)                                                  */
/*       HSX (0x20037072)                                                     */
/*       BDX (0x20037072)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS2_IIO_DFX_GLOBAL_REG 0x12012072
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x072
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* SLTCAP2_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x40037074)                                                  */
/*       IVT_EX (0x40037074)                                                  */
/*       HSX (0x40037074)                                                     */
/*       BDX (0x40037074)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP2_IIO_DFX_GLOBAL_REG 0x12014074
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x074
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RO, default = 1'b0  */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RO, default = 1'b0  */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RO, default = 1'b0  */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RO, default = 1'b0  */
    UINT32 hotplug_surprise : 1;
    /* hotplug_surprise - Bits[5:5], RO, default = 1'b0  */
    UINT32 hotplug_capable : 1;
    /* hotplug_capable - Bits[6:6], RO, default = 1'b0  */
    UINT32 slot_power_limit_value : 8;
    /* slot_power_limit_value - Bits[14:7], RO, default = 8'b00000000  */
    UINT32 slot_power_limit_scale : 2;
    /* slot_power_limit_scale - Bits[16:15], RO, default = 2'b00  */
    UINT32 electromechanical_interlock_present : 1;
    /* electromechanical_interlock_present - Bits[17:17], RO, default = 1'b0  */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0  */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RO, default = 13'b0000000000000  */
  } Bits;
  UINT32 Data;
} SLTCAP2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* SLTSTS2_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x2003707A)                                                  */
/*       IVT_EX (0x2003707A)                                                  */
/*       HSX (0x2003707A)                                                     */
/*       BDX (0x2003707A)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS2_IIO_DFX_GLOBAL_REG 0x1201207A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x07a
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RO, default = 1'b0  */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RO, default = 1'b0  */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RO, default = 1'b0  */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RO, default = 1'b0  */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO, default = 1'b0  */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO, default = 1'b0  */
    UINT16 electromechanical_latch_status : 1;
    /* electromechanical_latch_status - Bits[7:7], RO, default = 1'b0  */
    UINT16 data_link_layer_state_changed : 1;
    /* data_link_layer_state_changed - Bits[8:8], RO, default = 1'b0  */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */








/* DFX_HVM_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x2003711C)                                                  */
/*       IVT_EX (0x2003711C)                                                  */
/*       HSX (0x4003711C)                                                     */
/*       BDX (0x4003711C)                                                     */
/* Register default value on IVT_EP:    0x0800                                */
/* Register default value on IVT_EX:    0x0800                                */
/* Register default value on HSX:       0x000A0800                            */
/* Register default value on BDX:       0x000A0800                            */
#define DFX_HVM_IIO_DFX_GLOBAL_REG 0x1201C000


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x11c
 */
typedef union {
  struct {
    UINT32 short_rst : 1;
    /* short_rst - Bits[0:0], RW_L, default = 1'b0 
       Enables short reset for HVM testing. Counters are shortened in PCIe.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 digital_loopback : 1;
    /* digital_loopback - Bits[1:1], RW_L, default = 1'b0 
       Enables digital loopback for HVM testing
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_pllclkdistoff : 1;
    /* en_pllclkdistoff - Bits[2:2], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfg_invalid_dev_mmio_chk_dis : 1;
    /* cfg_invalid_dev_mmio_chk_dis - Bits[3:3], RW_L, default = 1'b0 
       Disables reads to invalid device/functions returning -1 and writes from being 
       dropped. When disabled, all writes will work if they hit an existing register 
       and reads return 0 unless hit an existing register. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 msgchan_gateclkdis : 1;
    /* msgchan_gateclkdis - Bits[4:4], RW_L, default = 1'b0 
       Disables clock gating for the message channel
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfg_clkgate_dis : 1;
    /* cfg_clkgate_dis - Bits[5:5], RW_L, default = 1'b0 
       Disables clock gating on the config logic.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfg_fastpath_dis : 1;
    /* cfg_fastpath_dis - Bits[6:6], RW_L, default = 1'b0 
       Disables fast path only on config ring. When enabled, decodes config transaction 
       and will send it down just the fast path if able. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 reutmbpenable : 1;
    /* reutmbpenable - Bits[7:7], RW_L, default = 1'b0 
       MBP to REUT Enable
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 free_delay_count : 4;
    /* free_delay_count - Bits[11:8], RW_L, default = 4'b1000 
       Provides backpressure on message channel to separate back to back transactions. 
       Set to zero to disable. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_msgchan_pmrsblock : 1;
    /* dis_msgchan_pmrsblock - Bits[12:12], RW_L, default = 1'b0 
       If 0, the PMRsBlock blocks traffic to the message channel bgf.
       If 1, the PMRsBlock does not traffic to the message channel bgf, and message 
       channel requests can be lost during GV flows. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cr_en_vpp_pwren : 1;
    /* cr_en_vpp_pwren - Bits[13:13], RW_L, default = 1'b0 
       When set, All Hotplug PWREN# will be asserted when VPP is disabled.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 spare_cfg : 2;
    /* spare_cfg - Bits[15:14], RW_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disable_msgchan_msi_ordering : 1;
    /* disable_msgchan_msi_ordering - Bits[16:16], RW_L, default = 1'b0 
       When 0, msg channel completions for requestors selected by msi_request_ord will 
       be ordered to message signalled interrupts. 
       When 1, msg channel completions for requestors selected by msi_request_ord will 
       not be ordered to message signalled interrupts. 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 msi_ordered_request : 1;
    /* msi_ordered_request - Bits[17:17], RW_L, default = 1'b1 
       When 0, all message channel operations with the .IA bit set will be orderable to 
       MSIs. 
       When 1, only message channel operations with a ubox srcid with the .IA bit set 
       will be orderable to MSIs. 
       disable_msgchan_msi_ordering must be 0 for this CSR to have an effect.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 msi_injection : 1;
    /* msi_injection - Bits[18:18], RW_L, default = 1'b0 
       When 1, enable short duration injections to the msg channel logic as if an MSI 
       were pending. 
       When 0, no injection is enabled.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 block_msgchan_bgf : 1;
    /* block_msgchan_bgf - Bits[19:19], RW_L, default = 1'b1 
       When 1, the IIMI msg channel wrapper blocks incoming msg channel requests at the 
       BGF and at the router. 
       When 0, the IIMI msg channel wrapper blocks incoming msg channel requests at the 
       router only. 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 12;
    /* rsvd - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFX_HVM_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */














/* IIMI_ERR_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x20037164)                                                  */
/*       IVT_EX (0x20037164)                                                  */
/*       HSX (0x20037164)                                                     */
/*       BDX (0x20037164)                                                     */
/* Register default value:              0x0000                                */
#define IIMI_ERR_IIO_DFX_GLOBAL_REG 0x12012164


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * This register allows debug signals to be observable on the Error[2:0] pins.
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 iiodbg_disable : 3;
    /* iiodbg_disable - Bits[5:3], RWS_L, default = 3'b000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT16 rsvd_6 : 3;
    /* rsvd_6 - Bits[8:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 dbg_sel : 1;
    /* dbg_sel - Bits[9:9], RWS_L, default = 1'b0 
       
       Notes;
       Locked by RSPLCK
     */
    UINT16 rvser : 6;
    /* rvser - Bits[15:10], RWS_L, default = 6'b000000 
       
       Notes:
       Locked by RSPLCK
     */
  } Bits;
  UINT16 Data;
} IIMI_ERR_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */






































/* CTS_DEBUG_INDEX_IIO_DFX_GLOBAL_REG supported on:                           */
/*       BDX (0x40037214)                                                     */
/* Register default value:              0x00000000                            */
#define CTS_DEBUG_INDEX_IIO_DFX_GLOBAL_REG 0x12014214

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * This register provides the index into the array of the registers used for the 
 * CTS instantiated in the IIO 
 */
typedef union {
  struct {
    UINT32 cts_reg_index : 9;
    /* cts_reg_index - Bits[8:0], RWS_L, default = 9'b000000000 
       selects the index & type of register operation
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_9 : 2;
    /* rsvd_9 - Bits[10:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 cts_reg_read : 1;
    /* cts_reg_read - Bits[11:11], RWS_L, default = 1'b0 
       set if we need to do a read
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cts_reg_write : 1;
    /* cts_reg_write - Bits[12:12], RWS_L, default = 1'b0 
       set if we need to do a write
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_13 : 19;
    /* rsvd_13 - Bits[31:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CTS_DEBUG_INDEX_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CTS_DEBUG_DATA_IIO_DFX_GLOBAL_REG supported on:                            */
/*       BDX (0x40037218)                                                     */
/* Register default value:              0x00000000                            */
#define CTS_DEBUG_DATA_IIO_DFX_GLOBAL_REG 0x12014218

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * This register provides the data contents  into the array of the registers used 
 * for the CTS instantiated in the IIO 
 */
typedef union {
  struct {
    UINT32 cts_reg_data : 32;
    /* cts_reg_data - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Has the read/write data for cts register read/write operations
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CTS_DEBUG_DATA_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */








/* TSWCTL1_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x40037308)                                                  */
/*       IVT_EX (0x40037308)                                                  */
/*       HSX (0x40037308)                                                     */
/*       BDX (0x40037308)                                                     */
/* Register default value on IVT_EP:    0x0000C3FC                            */
/* Register default value on IVT_EX:    0x0000C3FC                            */
/* Register default value on HSX:       0x000083FC                            */
/* Register default value on BDX:       0x000083FC                            */
#define TSWCTL1_IIO_DFX_GLOBAL_REG 0x12014308
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x308
 */
typedef union {
  struct {
    UINT32 jkt_mode_disable_rfofreeze : 1;
    /* jkt_mode_disable_rfofreeze - Bits[0:0], RW_L, default = 1'b0  */
    UINT32 jkt_mode_disable_cb_wrhdr_squish : 1;
    /* jkt_mode_disable_cb_wrhdr_squish - Bits[1:1], RW_L, default = 1'b0  */
    UINT32 np_pf_disable_global_cb : 1;
    /* np_pf_disable_global_cb - Bits[2:2], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 np_pf_disable_global_iou2 : 1;
    /* np_pf_disable_global_iou2 - Bits[3:3], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 np_pf_disable_global_dmi_vc0 : 1;
    /* np_pf_disable_global_dmi_vc0 - Bits[4:4], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 np_pf_disable_global_misc : 1;
    /* np_pf_disable_global_misc - Bits[5:5], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 np_pf_disable_global_non_vc0 : 1;
    /* np_pf_disable_global_non_vc0 - Bits[6:6], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 csr_atomic_tph_disable : 1;
    /* csr_atomic_tph_disable - Bits[7:7], RW_L, default = 1'b1  */
    UINT32 np_pf_disable_global_iou1 : 1;
    /* np_pf_disable_global_iou1 - Bits[8:8], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 gpe_routing_id : 1;
    /* gpe_routing_id - Bits[9:9], RW_L, default = 1'b1 
       This CSR is to select the MSB routing ID used for Assert/Deassert GPE VDMs sent 
       to the DMI interface. 
       
       '1' : r[2:0] = "100"
       '0' : r[2:0] = "000"
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 csr_vt_p_pf_arb_throttle_iou0 : 1;
    /* csr_vt_p_pf_arb_throttle_iou0 - Bits[10:10], RW_L, default = 1'b0  */
    UINT32 csr_vt_p_pf_arb_throttle_iou1 : 1;
    /* csr_vt_p_pf_arb_throttle_iou1 - Bits[11:11], RW_L, default = 1'b0  */
    UINT32 csr_vt_p_pf_arb_throttle_iou2 : 1;
    /* csr_vt_p_pf_arb_throttle_iou2 - Bits[12:12], RW_L, default = 1'b0  */
    UINT32 csr_vt_p_pf_arb_throttle_cbme : 1;
    /* csr_vt_p_pf_arb_throttle_cbme - Bits[13:13], RW_L, default = 1'b0  */
    UINT32 csr_cmp_opt_disable : 1;
    /* csr_cmp_opt_disable - Bits[14:14], RW_L, default = 1'b0  */
    UINT32 csr_dfx_vc1_vcm_conflic_fix : 1;
    /* csr_dfx_vc1_vcm_conflic_fix - Bits[15:15], RW_L, default = 1'b1 
       
       Notes:
       Fix for HSD 4541199
       1 : VC1/VCm P F arbitration policy gives priority on request for Data only vs. 
       Header 
       0 : VC1/VCm P F arbitration policy is round robin. No weighting based on Data 
       only 
       Locked by RSPLCK
     */
    UINT32 csr_dfx_no_new_np_pf_iou0 : 4;
    /* csr_dfx_no_new_np_pf_iou0 - Bits[19:16], RW_L, default = 4'b0000 
       IOU0 cluster NP prefetch heuristic mechanism
       
       bit[3:1]: Heuristic algorithm for throttling NP prefetch
       'b000: Disable all NP prefetches
       'b001: NP prefetch is stopped if P in each of the last two sets of 4 cycles 
       (1-4, 5-8 cycles ago) 
       'b010: NP prefetch is stopped if any P in the last 8 cycles
       'b011: NP prefetch is stopped if P in each of the last three sets of 4 cycles 
       (1-4, 5-8, 9-12 cycles ago) 
       'b100: NP prefetch is stopped if any P in the last 12 cycles
       'b101: NP prefetch is stopped if P in each of the last four sets of 4 cycles 
       (1-4, 5-8, 9-12, 13-16 cycles ago) 
       'b110: NP prefetch is stopped if P in each of the last two sets of 8 cycles (1-8 
       and 9-16 cycles ago) 
       'b111: NP prefetch is stopped if any P in the last 16 cycles
       
       bit[0]: Selection of posted for heuristic algorithm
       'b0: Tracking of posted based on posted request receiving grant
       'b1: Tracking of posted based on posted request arbitrating/bidding (more 
       stringent) 
     */
    UINT32 csr_dfx_no_new_np_pf_iou1 : 4;
    /* csr_dfx_no_new_np_pf_iou1 - Bits[23:20], RW_L, default = 4'b0000 
       IOU1 cluster NP prefetch heuristic mechanism
       
       bit[3:1]: Heuristic algorithm for throttling NP prefetch
       'b000: Disable all NP prefetches
       'b001: NP prefetch is stopped if P in each of the last two sets of 4 cycles 
       (1-4, 5-8 cycles ago) 
       'b010: NP prefetch is stopped if any P in the last 8 cycles
       'b011: NP prefetch is stopped if P in each of the last three sets of 4 cycles 
       (1-4, 5-8, 9-12 cycles ago) 
       'b100: NP prefetch is stopped if any P in the last 12 cycles
       'b101: NP prefetch is stopped if P in each of the last four sets of 4 cycles 
       (1-4, 5-8, 9-12, 13-16 cycles ago) 
       'b110: NP prefetch is stopped if P in each of the last two sets of 8 cycles (1-8 
       and 9-16 cycles ago) 
       'b111: NP prefetch is stopped if any P in the last 16 cycles
       
       bit[0]: Selection of posted for heuristic algorithm
       'b0: Tracking of posted based on posted request receiving grant
       'b1: Tracking of posted based on posted request arbitrating/bidding (more 
       stringent) 
     */
    UINT32 csr_dfx_no_new_np_pf_iou2 : 4;
    /* csr_dfx_no_new_np_pf_iou2 - Bits[27:24], RW_L, default = 4'b0000 
       IOU2 cluster NP prefetch heuristic mechanism
       
       bit[3:1]: Heuristic algorithm for throttling NP prefetch
       'b000: Disable all NP prefetches
       'b001: NP prefetch is stopped if P in each of the last two sets of 4 cycles 
       (1-4, 5-8 cycles ago) 
       'b010: NP prefetch is stopped if any P in the last 8 cycles
       'b011: NP prefetch is stopped if P in each of the last three sets of 4 cycles 
       (1-4, 5-8, 9-12 cycles ago) 
       'b100: NP prefetch is stopped if any P in the last 12 cycles
       'b101: NP prefetch is stopped if P in each of the last four sets of 4 cycles 
       (1-4, 5-8, 9-12, 13-16 cycles ago) 
       'b110: NP prefetch is stopped if P in each of the last two sets of 8 cycles (1-8 
       and 9-16 cycles ago) 
       'b111: NP prefetch is stopped if any P in the last 16 cycles
       
       bit[0]: Selection of posted for heuristic algorithm
       'b0: Tracking of posted based on posted request receiving grant
       'b1: Tracking of posted based on posted request arbitrating/bidding (more 
       stringent) 
     */
    UINT32 csr_dfx_no_new_np_pf_cbme : 4;
    /* csr_dfx_no_new_np_pf_cbme - Bits[31:28], RW_L, default = 4'b0000 
       CBDMA cluster NP prefetch heuristic mechanism
       
       bit[3:1]: Heuristic algorithm for throttling NP prefetch
       'b000: Disable all NP prefetches
       'b001: NP prefetch is stopped if P in each of the last two sets of 4 cycles 
       (1-4, 5-8 cycles ago) 
       'b010: NP prefetch is stopped if any P in the last 8 cycles
       'b011: NP prefetch is stopped if P in each of the last three sets of 4 cycles 
       (1-4, 5-8, 9-12 cycles ago) 
       'b100: NP prefetch is stopped if any P in the last 12 cycles
       'b101: NP prefetch is stopped if P in each of the last four sets of 4 cycles 
       (1-4, 5-8, 9-12, 13-16 cycles ago) 
       'b110: NP prefetch is stopped if P in each of the last two sets of 8 cycles (1-8 
       and 9-16 cycles ago) 
       'b111: NP prefetch is stopped if any P in the last 16 cycles
       
       bit[0]: Selection of posted for heuristic algorithm
       'b0: Tracking of posted based on posted request receiving grant
       'b1: Tracking of posted based on posted request arbitrating/bidding (more 
       stringent) 
     */
  } Bits;
  UINT32 Data;
} TSWCTL1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* TSWCTL0_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x4003730C)                                                  */
/*       IVT_EX (0x4003730C)                                                  */
/*       HSX (0x4003730C)                                                     */
/*       BDX (0x4003730C)                                                     */
/* Register default value:              0x0C11500C                            */
#define TSWCTL0_IIO_DFX_GLOBAL_REG 0x1201430C


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x30c
 */
typedef union {
  struct {
    UINT32 fastpath_disabled : 1;
    /* fastpath_disabled - Bits[0:0], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 disable_ns_read_pf : 1;
    /* disable_ns_read_pf - Bits[1:1], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 np_pf_disable_global_iou0 : 1;
    /* np_pf_disable_global_iou0 - Bits[2:2], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 me_disable : 1;
    /* me_disable - Bits[3:3], RWS_O, default = 1'b1  */
    UINT32 allow_ib_mmio_cfg : 1;
    /* allow_ib_mmio_cfg - Bits[4:4], RWS_O, default = 1'b0  */
    UINT32 ignore_acs_p2p_ma_lpbk : 1;
    /* ignore_acs_p2p_ma_lpbk - Bits[5:5], RW_O, default = 1'b0  */
    UINT32 rsvd_6 : 2;
    UINT32 csr_vlw_throttle_np_enable : 1;
    /* csr_vlw_throttle_np_enable - Bits[8:8], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 vlw_throttle_p_enable : 1;
    /* vlw_throttle_p_enable - Bits[9:9], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 global_nosnoop_disable : 1;
    /* global_nosnoop_disable - Bits[10:10], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 fp_2cyc_disable : 1;
    /* fp_2cyc_disable - Bits[11:11], RW_L, default = 1'b0 
       1
     */
    UINT32 disable_phold_np_dmi_p2p : 1;
    /* disable_phold_np_dmi_p2p - Bits[12:12], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_13 : 5;
    UINT32 convert_ob_ca_to_ma : 1;
    /* convert_ob_ca_to_ma - Bits[18:18], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 convert_ib_ca_to_ma : 1;
    /* convert_ib_ca_to_ma - Bits[19:19], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_20 : 3;
    UINT32 disrstptr : 1;
    /* disrstptr - Bits[23:23], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_24 : 2;
    UINT32 lock_target_np : 1;
    /* lock_target_np - Bits[26:26], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_27 : 5;
  } Bits;
  UINT32 Data;
} TSWCTL0_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */








/* ACA_ARB_PERF_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037320)                                                  */
/*       IVT_EX (0x40037320)                                                  */
/*       HSX (0x40037320)                                                     */
/*       BDX (0x40037320)                                                     */
/* Register default value:              0x00060F08                            */
#define ACA_ARB_PERF_IIO_DFX_GLOBAL_REG 0x12014320


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x320
 */
typedef union {
  struct {
    UINT32 enable_2nd_np_iou0 : 1;
    /* enable_2nd_np_iou0 - Bits[0:0], RW_L, default = 1'b0  */
    UINT32 enable_2nd_np_iou1 : 1;
    /* enable_2nd_np_iou1 - Bits[1:1], RW_L, default = 1'b0  */
    UINT32 enable_2nd_np_iou2 : 1;
    /* enable_2nd_np_iou2 - Bits[2:2], RW_L, default = 1'b0  */
    UINT32 enable_2nd_np_cbme0 : 1;
    /* enable_2nd_np_cbme0 - Bits[3:3], RW_L, default = 1'b1  */
    UINT32 enable_posted_vtd_arb_delay_iou0 : 1;
    /* enable_posted_vtd_arb_delay_iou0 - Bits[4:4], RW_L, default = 1'b0  */
    UINT32 enable_posted_vtd_arb_delay_iou1 : 1;
    /* enable_posted_vtd_arb_delay_iou1 - Bits[5:5], RW_L, default = 1'b0  */
    UINT32 enable_posted_vtd_arb_delay_iou2 : 1;
    /* enable_posted_vtd_arb_delay_iou2 - Bits[6:6], RW_L, default = 1'b0  */
    UINT32 enable_posted_vtd_arb_delay_cbme0 : 1;
    /* enable_posted_vtd_arb_delay_cbme0 - Bits[7:7], RW_L, default = 1'b0  */
    UINT32 enable_nonposted_vtd_arb_delay_iou0 : 1;
    /* enable_nonposted_vtd_arb_delay_iou0 - Bits[8:8], RW_L, default = 1'b1  */
    UINT32 enable_nonposted_vtd_arb_delay_iou1 : 1;
    /* enable_nonposted_vtd_arb_delay_iou1 - Bits[9:9], RW_L, default = 1'b1  */
    UINT32 enable_nonposted_vtd_arb_delay_iou2 : 1;
    /* enable_nonposted_vtd_arb_delay_iou2 - Bits[10:10], RW_L, default = 1'b1  */
    UINT32 enable_nonposted_vtd_arb_delay_cbme0 : 1;
    /* enable_nonposted_vtd_arb_delay_cbme0 - Bits[11:11], RW_L, default = 1'b1  */
    UINT32 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 disable_two_read : 1;
    /* disable_two_read - Bits[16:16], RW_L, default = 1'b0  */
    UINT32 diff_to_disable_alt_cpl : 5;
    /* diff_to_disable_alt_cpl - Bits[21:17], RW_L, default = 5'b00011  */
    UINT32 p2p_rd_256b_arb_dis : 1;
    /* p2p_rd_256b_arb_dis - Bits[22:22], RW_L, default = 1'b0  */
    UINT32 rsvd_23 : 9;
    /* rsvd_23 - Bits[31:23], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ACA_ARB_PERF_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */








/* TSWPXPTHRC1_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037330)                                                  */
/*       IVT_EX (0x40037330)                                                  */
/*       HSX (0x40037330)                                                     */
/*       BDX (0x40037330)                                                     */
/* Register default value:              0x00000000                            */
#define TSWPXPTHRC1_IIO_DFX_GLOBAL_REG 0x12014330
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x330
 */
typedef union {
  struct {
    UINT32 pxp0_asc_sel : 4;
    /* pxp0_asc_sel - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 pxp0_asc_en_np : 4;
    /* pxp0_asc_en_np - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 pxp0_asc_en_p : 4;
    /* pxp0_asc_en_p - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 pxp0_asc_en_cpl : 4;
    /* pxp0_asc_en_cpl - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 pxp1_asc_sel : 4;
    /* pxp1_asc_sel - Bits[19:16], RWS_L, default = 4'b0000  */
    UINT32 pxp1_asc_en_np : 4;
    /* pxp1_asc_en_np - Bits[23:20], RWS_L, default = 4'b0000  */
    UINT32 pxp1_asc_en_p : 4;
    /* pxp1_asc_en_p - Bits[27:24], RWS_L, default = 4'b0000  */
    UINT32 pxp1_asc_en_cpl : 4;
    /* pxp1_asc_en_cpl - Bits[31:28], RWS_L, default = 4'b0000  */
  } Bits;
  UINT32 Data;
} TSWPXPTHRC1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */










/* TSWDBGERRSTDIS0_IIO_DFX_GLOBAL_REG supported on:                           */
/*       IVT_EP (0x40037358)                                                  */
/*       IVT_EX (0x40037358)                                                  */
/*       HSX (0x40037358)                                                     */
/*       BDX (0x40037358)                                                     */
/* Register default value:              0x00000000                            */
#define TSWDBGERRSTDIS0_IIO_DFX_GLOBAL_REG 0x12014358
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x358
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 12;
    /* rsvd_0 - Bits[11:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pcie0ib_fifo_overflowdis : 4;
    /* pcie0ib_fifo_overflowdis - Bits[15:12], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 pcie0ib_fifo_underflowdis : 4;
    /* pcie0ib_fifo_underflowdis - Bits[19:16], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_20 : 4;
    /* rsvd_20 - Bits[23:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pcie1ib_fifo_underflowdis : 4;
    /* pcie1ib_fifo_underflowdis - Bits[27:24], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 pcie1ib_fifo_overflowdis : 4;
    /* pcie1ib_fifo_overflowdis - Bits[31:28], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
  } Bits;
  UINT32 Data;
} TSWDBGERRSTDIS0_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* TSWDBGERRSTDIS1_IIO_DFX_GLOBAL_REG supported on:                           */
/*       IVT_EP (0x4003735C)                                                  */
/*       IVT_EX (0x4003735C)                                                  */
/*       HSX (0x4003735C)                                                     */
/*       BDX (0x4003735C)                                                     */
/* Register default value:              0x00000000                            */
#define TSWDBGERRSTDIS1_IIO_DFX_GLOBAL_REG 0x1201435C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x35c
 */
typedef union {
  struct {
    UINT32 meob_underflowdis : 1;
    /* meob_underflowdis - Bits[0:0], RWS_L, default = 1'b0 
       1
     */
    UINT32 meob_overflowdis : 1;
    /* meob_overflowdis - Bits[1:1], RWS_L, default = 1'b0 
       1
     */
    UINT32 cbib_underflowdis_2 : 1;
    /* cbib_underflowdis_2 - Bits[2:2], RWS_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 cbib_overflowdis_2 : 1;
    /* cbib_overflowdis_2 - Bits[3:3], RWS_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_4 : 5;
    UINT32 dmipcieob_overflowdis : 5;
    /* dmipcieob_overflowdis - Bits[13:9], RWS_L, default = 5'b00000 
       1
     */
    UINT32 dmipcieib_underflowdis : 5;
    /* dmipcieib_underflowdis - Bits[18:14], RWS_L, default = 5'b00000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 dmipcieib_overflowdis : 5;
    /* dmipcieib_overflowdis - Bits[23:19], RWS_L, default = 5'b00000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 cbn_underflowdis : 2;
    /* cbn_underflowdis - Bits[25:24], RWS_L, default = 2'b00 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 cbn_overflowdis : 2;
    /* cbn_overflowdis - Bits[27:26], RWS_L, default = 2'b00 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 cb_rddata_underflowdis : 1;
    /* cb_rddata_underflowdis - Bits[28:28], RWS_L, default = 1'b0 
       1
     */
    UINT32 cb_rddata_overflowdis : 1;
    /* cb_rddata_overflowdis - Bits[29:29], RWS_L, default = 1'b0 
       1
     */
    UINT32 cb_desc_underflowdis : 1;
    /* cb_desc_underflowdis - Bits[30:30], RWS_L, default = 1'b0 
       1
     */
    UINT32 cb_desc_overflowdis : 1;
    /* cb_desc_overflowdis - Bits[31:31], RWS_L, default = 1'b0 
       1
     */
  } Bits;
  UINT32 Data;
} TSWDBGERRSTDIS1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */








/* TSWDBGFIFOSTAT1_IIO_DFX_GLOBAL_REG supported on:                           */
/*       IVT_EP (0x40037374)                                                  */
/*       IVT_EX (0x40037374)                                                  */
/*       HSX (0x40037374)                                                     */
/*       BDX (0x40037374)                                                     */
/* Register default value:              0x00000000                            */
#define TSWDBGFIFOSTAT1_IIO_DFX_GLOBAL_REG 0x12014374
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x374
 */
typedef union {
  struct {
    UINT32 me_fifo_status_bits : 5;
    /* me_fifo_status_bits - Bits[4:0], RW1CS, default = 5'b00000  */
    UINT32 dmipcie_fifo_status_bits : 13;
    /* dmipcie_fifo_status_bits - Bits[17:5], RW1CS, default = 13'b0000000000000  */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TSWDBGFIFOSTAT1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */






/* JUNKREG4_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037380)                                                  */
/*       IVT_EX (0x40037380)                                                  */
/*       HSX (0x40037380)                                                     */
/*       BDX (0x40037380)                                                     */
/* Register default value:              0x00000000                            */
#define JUNKREG4_IIO_DFX_GLOBAL_REG 0x12014380


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x380
 */
typedef union {
  struct {
    UINT32 csr_s_pstate_delay : 19;
    /* csr_s_pstate_delay - Bits[18:0], RW_L, default = 19'b0000000000000000000  */
    UINT32 rsvd : 13;
    /* rsvd - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} JUNKREG4_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CSIPISOCRES_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037388)                                                  */
/*       IVT_EX (0x40037388)                                                  */
/*       HSX (0x40037388)                                                     */
/*       BDX (0x40037388)                                                     */
/* Register default value:              0x00000000                            */
#define CSIPISOCRES_IIO_DFX_GLOBAL_REG 0x12014388


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x388
 */
typedef union {
  struct {
    UINT32 vcp_maximum : 4;
    /* vcp_maximum - Bits[3:0], RW_L, default = 4'b0000  */
    UINT32 vcp_reserved : 4;
    /* vcp_reserved - Bits[7:4], RW_L, default = 4'b0000  */
    UINT32 vc1_maximum : 4;
    /* vc1_maximum - Bits[11:8], RW_L, default = 4'b0000  */
    UINT32 vc1_reserved : 4;
    /* vc1_reserved - Bits[15:12], RW_L, default = 4'b0000  */
    UINT32 isoc_enabled : 1;
    /* isoc_enabled - Bits[16:16], RW_L, default = 1'b0 
       This is the isoch enabled bit to enable the isoch reserved entry programmed in 
       vc1_reserved, vc1_maximum, vcp_reserved and vcp_maximum 
     */
    UINT32 merge_vc0_cnt : 1;
    /* merge_vc0_cnt - Bits[17:17], RW_L, default = 1'b0 
       If set, revert to legacy behavior of comparing max_cache_vc0 to total cache 
       usage instead of VC0 cache usage. 
     */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CSIPISOCRES_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */












/* MAX_FC0_IIO_DFX_GLOBAL_REG supported on:                                   */
/*       IVT_EP (0x400373B8)                                                  */
/*       IVT_EX (0x400373B8)                                                  */
/*       HSX (0x400373B8)                                                     */
/*       BDX (0x400373B8)                                                     */
/* Register default value:              0x00000000                            */
#define MAX_FC0_IIO_DFX_GLOBAL_REG 0x120143B8


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x3b8
 */
typedef union {
  struct {
    UINT32 maxpiou2 : 4;
    /* maxpiou2 - Bits[3:0], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 maxnpiou2 : 4;
    /* maxnpiou2 - Bits[7:4], RWS_L, default = 4'b0000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 maxpiou1 : 4;
    /* maxpiou1 - Bits[11:8], RWS_L, default = 4'b0000 
       1
     */
    UINT32 maxnpiou1 : 4;
    /* maxnpiou1 - Bits[15:12], RWS_L, default = 4'b0000 
       1
     */
    UINT32 maxpiou0 : 4;
    /* maxpiou0 - Bits[19:16], RWS_L, default = 4'b0000 
       1
     */
    UINT32 maxnpiou0 : 4;
    /* maxnpiou0 - Bits[23:20], RWS_L, default = 4'b0000 
       1
     */
    UINT32 discsiforwprog : 1;
    /* discsiforwprog - Bits[24:24], RWS_L, default = 1'b0 
       1
     */
    UINT32 no_forw_prog : 1;
    /* no_forw_prog - Bits[25:25], RWS_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 dismsgfp : 1;
    /* dismsgfp - Bits[26:26], RWS_L, default = 1'b0 
       1
     */
    UINT32 dislockforwprog : 1;
    /* dislockforwprog - Bits[27:27], RWS_L, default = 1'b0 
       1
     */
    UINT32 disintraforwprog : 1;
    /* disintraforwprog - Bits[28:28], RWS_L, default = 1'b0 
       1
     */
    UINT32 disinterforwprog : 1;
    /* disinterforwprog - Bits[29:29], RWS_L, default = 1'b0 
       1
     */
    UINT32 block_cache_le4_3cyc : 1;
    /* block_cache_le4_3cyc - Bits[30:30], RWS_L, default = 1'b0 
       Block arbitration to a given IRP set for 3 cycles after a winner when there are 
       <= 4 IRP entries available in that set (instead of 1 cycle). 
     */
    UINT32 rsvd : 1;
    /* rsvd - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MAX_FC0_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */








/* SWDBGCTL0_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373C4)                                                  */
/*       IVT_EX (0x400373C4)                                                  */
/*       HSX (0x400373C4)                                                     */
/*       BDX (0x400373C4)                                                     */
/* Register default value on IVT_EP:    0x004007FF                            */
/* Register default value on IVT_EX:    0x004007FF                            */
/* Register default value on HSX:       0x05C007FF                            */
/* Register default value on BDX:       0x05C007FF                            */
#define SWDBGCTL0_IIO_DFX_GLOBAL_REG 0x120143C4


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x3c4
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 11;
    UINT32 rsvd_11 : 1;
    /* rsvd_11 - Bits[11:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 set_dmi_cfg_type0 : 1;
    /* set_dmi_cfg_type0 - Bits[12:12], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_clusx_pri_deadlock_c : 1;
    /* dis_clusx_pri_deadlock_c - Bits[13:13], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 csifc_deadlock_en_c : 1;
    /* csifc_deadlock_en_c - Bits[14:14], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_15 : 7;
    /* rsvd_15 - Bits[21:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 enable_irp_intlv : 1;
    /* enable_irp_intlv - Bits[22:22], RW_L, default = 1'b1 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 enable_irp_set : 1;
    /* enable_irp_set - Bits[23:23], RW_L, default = 1'b1  */
    UINT32 rsvd_24 : 8;
  } Bits;
  UINT32 Data;
} SWDBGCTL0_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */






/* SPARE_SWEAST_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x400373D8)                                                  */
/*       IVT_EX (0x400373D8)                                                  */
/*       HSX (0x400373D8)                                                     */
/*       BDX (0x400373D8)                                                     */
/* Register default value:              0x3FFF0000                            */
#define SPARE_SWEAST_IIO_DFX_GLOBAL_REG 0x120143D8


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x3d8
 */
typedef union {
  struct {
    UINT32 locks_use_quiesce_flow : 1;
    /* locks_use_quiesce_flow - Bits[0:0], RW_L, default = 1'b0 
       Force lock/splitlock flows to behave like quiesce flows internally (fetch 
       pointers must advance to vt pf pointers, instead of just prefetch pointers). 
     */
    UINT32 locks_skip_vtd_check : 1;
    /* locks_skip_vtd_check - Bits[1:1], RW_L, default = 1'b0 
       Disable checking for a reserved VTd entry available for posted fetch translation 
       requests from a locked port at the start of the lock/splitlock/quiesce flows. 
     */
    UINT32 spare_csr_0 : 14;
    /* spare_csr_0 - Bits[15:2], RW_L, default = 14'b00000000000000  */
    UINT32 disable_ro_override : 1;
    /* disable_ro_override - Bits[16:16], RW_L, default = 1'b1  */
    UINT32 spare_csr_1 : 13;
    /* spare_csr_1 - Bits[29:17], RW_L, default = 13'b1111111111111  */
    UINT32 viral_autoack : 2;
    /* viral_autoack - Bits[31:30], RW_L, default = 2'b00 
       "00": Default: A0 behavior: only auto-ack Reset_warn during viral
       "01": Auto-ack all GO_S* messages incl. Reset_warn (i.e. DMICTRL.AUTOCOMPLETE_PM 
       behavior) 
       When the bit is set, the corresponding ring messages are dropped (auto-ack sent 
       to DMI) 
       "10": Do not auto-ack any Go_S* messages incl. Reset_warn.
       Allow messages to propagate to ring and ack to propagate downstream to DMI
       "11": Illegal case. This is reserved.
       
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} SPARE_SWEAST_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* SPARE_SWWEST_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x400373DC)                                                  */
/*       IVT_EX (0x400373DC)                                                  */
/*       HSX (0x400373DC)                                                     */
/*       BDX (0x400373DC)                                                     */
/* Register default value:              0xFFE00000                            */
#define SPARE_SWWEST_IIO_DFX_GLOBAL_REG 0x120143DC


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x3dc
 */
typedef union {
  struct {
    UINT32 ns_with_ro_disable : 1;
    /* ns_with_ro_disable - Bits[0:0], RW_L, default = 1'b0 
       
       '0' : Enable mode for No-Snoop with Relax Ordering
       '1' : Disable mode for No-Snoop with Relax Ordering
       
       Locked by DBGBUSLCK
     */
    UINT32 disable_intr_in_viral : 1;
    /* disable_intr_in_viral - Bits[1:1], RW, default = 1'b0 
       
       '0' : Enable interrupts in viral mode from APIC subagent
       '1' : Disable interrupts in viral mode from APIC subagent
       
     */
    UINT32 disable_pm_resp_in_viral : 1;
    /* disable_pm_resp_in_viral - Bits[2:2], RW, default = 1'b0 
       
       '0' : Enable PM_RESP from DMI to flow during viral mode.
       '1' : Disable PM_RESP from DMI to flow during viral mode.
       
     */
    UINT32 enable_vlw_in_viral : 1;
    /* enable_vlw_in_viral - Bits[3:3], RW, default = 1'b0 
       
       '0' : Disable VLW from DMI to flow during viral mode.
       '1' : Enable VLW from DMI to flow during viral mode.
       
     */
    UINT32 cache_avail_eff_lef4_sel : 1;
    /* cache_avail_eff_lef4_sel - Bits[4:4], RW_L, default = 1'b0 
       
       '0': Cache avail relative to max_cache_vc0 when isoc is enabled else relative to 
       max_cache 
       '1': Cache avail relative to max_cache
       
       Locked by DBGBUSLCK
     */
    UINT32 maxpiou1_x16 : 4;
    /* maxpiou1_x16 - Bits[8:5], RW_L, default = 4'b0000 
       Maximum number of posted transactions allowed for IOU1 as x16.
       Value is computed as {maxpiou1_x16[3:0], 2'h0}
     */
    UINT32 maxpiou0_x16 : 4;
    /* maxpiou0_x16 - Bits[12:9], RW_L, default = 4'b0000 
       Maximum number of posted transactions allowed for IOU0 as x16.
       Value is computed as {maxpiou0_x16[3:0], 2'h0}
     */
    UINT32 x16_ptq_ptr_depth : 7;
    /* x16_ptq_ptr_depth - Bits[19:13], RW_L, default = 7'b0000000 
       Programmable PTQ pointer depth used for x16 port. Needs to be enabled by 
       x16_ptq_ptr_depth_enable. Legal values are 1-64. 
       
       Locked by DBGBUSLCK
     */
    UINT32 x16_ptq_ptr_depth_enable : 1;
    /* x16_ptq_ptr_depth_enable - Bits[20:20], RW_L, default = 1'b0 
       PTQ pointer depth enable used for x16 ports only
       
       '0': Disable programmable PTQ pointer depth for x16 port. Depth will be 7'd64.
       '1': Enable programmable PTQ pointer depth for x16 port.
       
       Locked by DBGBUSLCK
     */
    UINT32 spare_csr : 10;
    /* spare_csr - Bits[30:21], RW_L, default = 10'b1111111111  */
    UINT32 disable_ro_override : 1;
    /* disable_ro_override - Bits[31:31], RW_L, default = 1'b1  */
  } Bits;
  UINT32 Data;
} SPARE_SWWEST_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */














/* FWDPROGRESS0_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037400)                                                  */
/*       IVT_EX (0x40037400)                                                  */
/*       HSX (0x40037400)                                                     */
/*       BDX (0x40037400)                                                     */
/* Register default value:              0x00FFFFA4                            */
#define FWDPROGRESS0_IIO_DFX_GLOBAL_REG 0x12014400
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x400
 */
typedef union {
  struct {
    UINT32 trans_enable : 1;
    /* trans_enable - Bits[0:0], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 timeout_enable : 1;
    /* timeout_enable - Bits[1:1], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 transtimeouten : 1;
    /* transtimeouten - Bits[2:2], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 trans_max : 5;
    /* trans_max - Bits[7:3], RW_L, default = 5'b10100 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 arb_timeout_val : 16;
    /* arb_timeout_val - Bits[23:8], RW_L, default = 16'b1111111111111111 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_24 : 1;
    /* rsvd_24 - Bits[24:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 iou2x16pri : 1;
    /* iou2x16pri - Bits[25:25], RW_L, default = 1'b0 
       1
     */
    UINT32 inbarbbackoff : 4;
    /* inbarbbackoff - Bits[29:26], RW_L, default = 4'b0000 
       1
     */
    UINT32 rsvd_30 : 2;
    /* rsvd_30 - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} FWDPROGRESS0_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* FWDPROGRESS1_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037404)                                                  */
/*       IVT_EX (0x40037404)                                                  */
/*       HSX (0x40037404)                                                     */
/*       BDX (0x40037404)                                                     */
/* Register default value:              0x20000000                            */
#define FWDPROGRESS1_IIO_DFX_GLOBAL_REG 0x12014404
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x404
 */
typedef union {
  struct {
    UINT32 arbstarvepri : 6;
    /* arbstarvepri - Bits[5:0], RW_L, default = 6'b000000 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 disable_new_jkt_bypassarb_mode : 1;
    /* disable_new_jkt_bypassarb_mode - Bits[6:6], RW, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd_7 : 1;
    /* rsvd_7 - Bits[7:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 disforwardprgs : 4;
    /* disforwardprgs - Bits[11:8], RW_L, default = 4'b0000 
       1
     */
    UINT32 rsvd_12 : 17;
    /* rsvd_12 - Bits[28:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 aggrnp_f_w_pf : 1;
    /* aggrnp_f_w_pf - Bits[29:29], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 disbypass : 2;
    /* disbypass - Bits[31:30], RW_L, default = 2'b00 
       
       Notes:
       Locked by RSPLCK
     */
  } Bits;
  UINT32 Data;
} FWDPROGRESS1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CSIPOOLDFX0_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037408)                                                  */
/*       IVT_EX (0x40037408)                                                  */
/*       HSX (0x40037408)                                                     */
/*       BDX (0x40037408)                                                     */
/* Register default value on IVT_EP:    0x64606460                            */
/* Register default value on IVT_EX:    0x64606460                            */
/* Register default value on HSX:       0x3C383C38                            */
/* Register default value on BDX:       0x3C383C38                            */
#define CSIPOOLDFX0_IIO_DFX_GLOBAL_REG 0x12014408
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x408
 */
typedef union {
  struct {
    UINT32 vc0_max_cache : 8;
    /* vc0_max_cache - Bits[7:0], RW_L, default = 8'b00111000 
       Limits how many VC0 transactions the switch can have active to a particular 
       set/way of IRP. It is unclear if switch will ever go over this limit; the 
       following constraints assume that it does not. 
       
       Applicable constraints:
       
       // VC0 traffic should leave room for isoch if isoch is on
       // IIO internally ignores bit 0
       if( csipisocres.isoc_enabled ) {
       csipooldfx0.vc0_max_cache <= (csipooldfx1.max_cache - 1)
       csipooldfx0.vc0_max_cache[0] == 0
       }
     */
    UINT32 max_cache_np : 8;
    /* max_cache_np - Bits[15:8], RW_L, default = 8'b00111100 
       Limits how many non-posted transactions the switch can have active to a 
       particular set/way of IRP. Switch is known to go up to 2 over this limit in 
       certain corner cases (but in the common case will limit itself to this number). 
       
       Applicable constraints:
       
       // NP must leave 1 entry for P
       (csipooldfx0.max_cache_np + 2) <= (csipooldfx1.max_cache - 1)
       
       // NP must be able to issue something
       csipooldfx0.max_cache_np > 0
     */
    UINT32 max_cache_np_pf : 8;
    /* max_cache_np_pf - Bits[23:16], RW_L, default = 8'b00111000 
       Limits how many non-posted prefetches the switch can have active to a particular 
       set/way of IRP. Switch is known to go up to 2 over this limit in certain corner 
       cases (but in the common case will limit itself to this number). 
       
       Applicable constraints:
       
       // NP prefetch must leave 1 entry for NP F
       // NP prefetch must be able to issue something if enabled
       if( (tswctl0.np_pf_disable_global_iou0 == 0) |
       (tswctl1.np_pf_disable_global_iou1 == 0) |
       (tswctl1.np_pf_disable_global_iou2 == 0) |
       (tswctl1.np_pf_disable_global_dmi_vc0 == 0) |
       (tswctl1.np_pf_disable_global_non_vc0 == 0) |
       (tswctl1.np_pf_disable_global_cb == 0) |
       (tswctl1.np_pf_disable_global_misc == 0) )
       {
       (csipooldfx0.max_cache_np_pf + 2) <= (csipooldfx0.max_cache_np - 1)
       csipooldfx0.max_cache_np_pf > 0
       }
     */
    UINT32 max_cache_p : 8;
    /* max_cache_p - Bits[31:24], RW_L, default = 8'b00111100 
       Limits how many posted prefetches the switch can have active to a particular 
       set/way of IRP. Switch is known to go up to 2 over this limit in certain corner 
       cases (but in the common case will limit itself to this number). 
       
       Applicable constraints:
       
       // P prefetch must leave 1 entry for P F and 1 entry for NP F
       (csipooldfx0.max_cache_p + 2) <= (csipooldfx1.max_cache - 2)
       
       // P prefetch must be able to issue something
       csipooldfx0.max_cache_p > 0
     */
  } Bits;
  UINT32 Data;
} CSIPOOLDFX0_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CSIPOOLDFX1_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x4003740C)                                                  */
/*       IVT_EX (0x4003740C)                                                  */
/*       HSX (0x4003740C)                                                     */
/*       BDX (0x4003740C)                                                     */
/* Register default value on IVT_EP:    0x6800000F                            */
/* Register default value on IVT_EX:    0x6800000F                            */
/* Register default value on HSX:       0x4000000F                            */
/* Register default value on BDX:       0x4000000F                            */
#define CSIPOOLDFX1_IIO_DFX_GLOBAL_REG 0x1201440C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x40c
 */
typedef union {
  struct {
    UINT32 orballownppfgt : 4;
    /* orballownppfgt - Bits[3:0], RW_L, default = 4'b1111  */
    UINT32 rsvd : 20;
    /* rsvd - Bits[23:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 max_cache : 8;
    /* max_cache - Bits[31:24], RW_L, default = 8'b01000000 
       Limits how many total transactions the switch can have active to a particular 
       set/way of IRP. It is unclear if switch will ever go over this limit; the 
       following constraints assume that it does not. 
       
       Applicable constraints:
       
       // Don't use more entries than IRP has available
       csipooldfx1.max_cache <= (8 * popcnt(irp_misc_dfx0.ctagentry_avail_mask))
     */
  } Bits;
  UINT32 Data;
} CSIPOOLDFX1_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
























/* ARB_CONTROL0_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x4003743C)                                                  */
/*       IVT_EX (0x4003743C)                                                  */
/*       HSX (0x4003743C)                                                     */
/*       BDX (0x4003743C)                                                     */
/* Register default value:              0x00000000                            */
#define ARB_CONTROL0_IIO_DFX_GLOBAL_REG 0x1201443C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x43c
 */
typedef union {
  struct {
    UINT32 pri_p_f_2slots_iou2 : 1;
    /* pri_p_f_2slots_iou2 - Bits[0:0], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 pri_p_f_2slots_iou1 : 1;
    /* pri_p_f_2slots_iou1 - Bits[1:1], RW_L, default = 1'b0 
       1
     */
    UINT32 pri_p_f_2slots_iou0 : 1;
    /* pri_p_f_2slots_iou0 - Bits[2:2], RW_L, default = 1'b0 
       1
     */
    UINT32 pri_p_f_2slots_misc6 : 1;
    /* pri_p_f_2slots_misc6 - Bits[3:3], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 pri_p_f_2slots_cbme0 : 1;
    /* pri_p_f_2slots_cbme0 - Bits[4:4], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 dis_pri_bak_iou2 : 1;
    /* dis_pri_bak_iou2 - Bits[5:5], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 dis_pri_bak_iou1 : 1;
    /* dis_pri_bak_iou1 - Bits[6:6], RW_L, default = 1'b0 
       1
     */
    UINT32 dis_pri_bak_iou0 : 1;
    /* dis_pri_bak_iou0 - Bits[7:7], RW_L, default = 1'b0 
       1
     */
    UINT32 dis_pri_bak_misc6 : 1;
    /* dis_pri_bak_misc6 - Bits[8:8], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 dis_pri_bak_cbme0 : 1;
    /* dis_pri_bak_cbme0 - Bits[9:9], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 adv_pri2_arb_iou2 : 1;
    /* adv_pri2_arb_iou2 - Bits[10:10], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 adv_pri2_arb_iou1 : 1;
    /* adv_pri2_arb_iou1 - Bits[11:11], RW_L, default = 1'b0 
       1
     */
    UINT32 adv_pri2_arb_iou0 : 1;
    /* adv_pri2_arb_iou0 - Bits[12:12], RW_L, default = 1'b0 
       1
     */
    UINT32 adv_pri2_arb_misc6 : 1;
    /* adv_pri2_arb_misc6 - Bits[13:13], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 adv_pri2_arb_cbme0 : 1;
    /* adv_pri2_arb_cbme0 - Bits[14:14], RW_L, default = 1'b0 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 sec_pri2_dis_iou1 : 4;
    /* sec_pri2_dis_iou1 - Bits[18:15], RW_L, default = 4'b0000 
       1
     */
    UINT32 sec_pri2_dis_iou0 : 4;
    /* sec_pri2_dis_iou0 - Bits[22:19], RW_L, default = 4'b0000 
       1
     */
    UINT32 pri_stall_arb_iou2 : 2;
    /* pri_stall_arb_iou2 - Bits[24:23], RW_L, default = 2'b00 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 pri_stall_arb_iou1 : 2;
    /* pri_stall_arb_iou1 - Bits[26:25], RW_L, default = 2'b00 
       1
     */
    UINT32 pri_stall_arb_iou0 : 2;
    /* pri_stall_arb_iou0 - Bits[28:27], RW_L, default = 2'b00 
       1
     */
    UINT32 pri_stall_arb_misc6 : 2;
    /* pri_stall_arb_misc6 - Bits[30:29], RW_L, default = 2'b00 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd : 1;
    /* rsvd - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ARB_CONTROL0_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */






/* ARB_CONTROL3_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037448)                                                  */
/*       IVT_EX (0x40037448)                                                  */
/*       HSX (0x40037448)                                                     */
/*       BDX (0x40037448)                                                     */
/* Register default value:              0x00000000                            */
#define ARB_CONTROL3_IIO_DFX_GLOBAL_REG 0x12014448
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x448
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 30;
    UINT32 extra : 2;
    /* extra - Bits[31:30], RWS, default = 2'b00  */
  } Bits;
  UINT32 Data;
} ARB_CONTROL3_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */














/* DBG_MUX14_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037484)                                                  */
/*       IVT_EX (0x40037484)                                                  */
/*       HSX (0x40037484)                                                     */
/*       BDX (0x40037484)                                                     */
/* Register default value:              0x00000000                            */
#define DBG_MUX14_IIO_DFX_GLOBAL_REG 0x12014484


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x484
 */
typedef union {
  struct {
    UINT32 ptq_ptr_sel_tswac_cbme : 2;
    /* ptq_ptr_sel_tswac_cbme - Bits[1:0], RWS_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 ptq_ptr_sel_tswac_iou2 : 2;
    /* ptq_ptr_sel_tswac_iou2 - Bits[3:2], RWS_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 ptq_ptr_sel_tswac_iou1 : 2;
    /* ptq_ptr_sel_tswac_iou1 - Bits[5:4], RWS_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 ptq_ptr_sel_tswac_iou0 : 2;
    /* ptq_ptr_sel_tswac_iou0 - Bits[7:6], RWS_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 sel_addr_tswidp : 2;
    /* sel_addr_tswidp - Bits[9:8], RWS_L, default = 2'b00 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DBG_MUX14_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */


































/* DBG_MUX40_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374F0)                                                  */
/*       IVT_EX (0x400374F0)                                                  */
/*       HSX (0x400374F0)                                                     */
/*       BDX (0x400374F0)                                                     */
/* Register default value:              0x00000000                            */
#define DBG_MUX40_IIO_DFX_GLOBAL_REG 0x120144F0


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x4f0
 */
typedef union {
  struct {
    UINT32 rsvd : 31;
    /* rsvd - Bits[30:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pribar45_hit_dbgrng_sel : 1;
    /* pribar45_hit_dbgrng_sel - Bits[31:31], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DBG_MUX40_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* PSMI_HVM_GLOBAL_REG_IIO_DFX_GLOBAL_REG supported on:                       */
/*       IVT_EP (0x40037500)                                                  */
/*       IVT_EX (0x40037500)                                                  */
/*       HSX (0x40037500)                                                     */
/*       BDX (0x40037500)                                                     */
/* Register default value:              0x80000018                            */
#define PSMI_HVM_GLOBAL_REG_IIO_DFX_GLOBAL_REG 0x12014500
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x500
 */
typedef union {
  struct {
    UINT32 psmi_capture_mode : 1;
    /* psmi_capture_mode - Bits[0:0], RW_L, default = 1'b0 
       Notes:
       Locked by SPARELCK
     */
    UINT32 psmi_replay_mode : 1;
    /* psmi_replay_mode - Bits[1:1], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 psmi_wipe_disable : 1;
    /* psmi_wipe_disable - Bits[2:2], RW_L, default = 1'b0 
       If this bit is set, then the PSMI Wipe signal is gated in the IIO cluster.
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd_3 : 6;
    UINT32 psmi_mode : 1;
    /* psmi_mode - Bits[9:9], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_10 : 15;
    UINT32 psmi_delay_reg : 3;
    /* psmi_delay_reg - Bits[27:25], RW_L, default = 3'b000 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_28 : 1;
    /* rsvd_28 - Bits[28:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rsvd_29 : 1;
    UINT32 rsvd_30 : 1;
    /* rsvd_30 - Bits[30:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 enable_pwrmtr : 1;
    /* enable_pwrmtr - Bits[31:31], RWS, default = 1'b1 
       1
     */
  } Bits;
  UINT32 Data;
} PSMI_HVM_GLOBAL_REG_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* IIO_DFX_LCK_CTL_CSR_IIO_DFX_GLOBAL_REG supported on:                       */
/*       IVT_EP (0x20037504)                                                  */
/*       IVT_EX (0x20037504)                                                  */
/*       HSX (0x20037504)                                                     */
/*       BDX (0x20037504)                                                     */
/* Register default value:              0x0000                                */
#define IIO_DFX_LCK_CTL_CSR_IIO_DFX_GLOBAL_REG 0x12012504


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x504
 */
typedef union {
  struct {
    UINT16 dbgbuslck : 1;
    /* dbgbuslck - Bits[0:0], RW_O, default = 1'b0 
       This bit locks accesses to the Debug bus control registers when set. Reads are 
       allowed even when the registers are locked. 
       
       This is AND'd with the similarly named bit in the IIO_DFX_LCK_CTL uCR register.
       
       BIOS must write this register after reset.
     */
    UINT16 asclck : 1;
    /* asclck - Bits[1:1], RW_O, default = 1'b0 
       This bit locks accesses to the ASC control registers when set. Reads are allowed 
       even when the registers are locked. 
       
       This is AND'd with the similarly named bit in the IIO_DFX_LCK_CTL uCR register.
       
       BIOS must write this register after reset.
     */
    UINT16 noalck : 1;
    /* noalck - Bits[2:2], RW_O, default = 1'b0 
       This bit locks accesses to the NOA control registers when set. Reads are allowed 
       even when the registers are locked. 
       
       This is AND'd with the similarly named bit in the IIO_DFX_LCK_CTL uCR register.
       
       BIOS must write this register after reset.
     */
    UINT16 rsplck : 1;
    /* rsplck - Bits[3:3], RW_O, default = 1'b0 
       This bit locks accesses to the response logic control registers when set. Reads 
       are allowed even when the registers are locked. 
       
       This is AND'd with the similarly named bit in the IIO_DFX_LCK_CTL uCR register.
       
       BIOS must write this register after reset.
     */
    UINT16 sparelck : 1;
    /* sparelck - Bits[4:4], RW_O, default = 1'b0 
       This bit locks accesses to the spare control registers when set. Reads are 
       allowed even when the registers are locked. 
       
       This is AND'd with the similarly named bit in the IIO_DFX_LCK_CTL uCR register.
       
       BIOS must write this register after reset.
     */
    UINT16 rsvd_5 : 2;
    UINT16 dfxuniphylck : 1;
    /* dfxuniphylck - Bits[7:7], RW_O, default = 1'b0  */
    UINT16 ntblck : 1;
    /* ntblck - Bits[8:8], RW_O, default = 1'b0 
       This bit locks writes to NTB config registers when set. Reads are always 
       allowed. 
       This is AND'ed with the similarly named bit in IIO_DFX_LCK_CTL. BIOS must write 
       this register after reset. 
     */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} IIO_DFX_LCK_CTL_CSR_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */














/* STAGGER_GLOBAL_REG_IIO_DFX_GLOBAL_REG supported on:                        */
/*       IVT_EP (0x40037524)                                                  */
/*       IVT_EX (0x40037524)                                                  */
/*       HSX (0x40037524)                                                     */
/*       BDX (0x40037524)                                                     */
/* Register default value:              0x00000002                            */
#define STAGGER_GLOBAL_REG_IIO_DFX_GLOBAL_REG 0x12014524
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x524
 */
typedef union {
  struct {
    UINT32 en_port_staggering : 1;
    /* en_port_staggering - Bits[0:0], RW_O, default = 1'b0  */
    UINT32 tx_stgr_sqcntr : 4;
    /* tx_stgr_sqcntr - Bits[4:1], RW_L, default = 4'b0001  */
    UINT32 rsvd : 27;
    /* rsvd - Bits[31:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} STAGGER_GLOBAL_REG_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* MISC_COMMON1_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037540)                                                  */
/*       IVT_EX (0x40037540)                                                  */
/*       HSX (0x40037540)                                                     */
/*       BDX (0x40037540)                                                     */
/* Register default value on IVT_EP:    0x00000003                            */
/* Register default value on IVT_EX:    0x00000003                            */
/* Register default value on HSX:       0x00000000                            */
/* Register default value on BDX:       0x00000000                            */
#define MISC_COMMON1_IIO_DFX_GLOBAL_REG 0x12014540


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x540
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dbg_mux_ntl_comp : 1;
    /* dbg_mux_ntl_comp - Bits[3:3], RW, default = 1'b0 
       When set, output ntl result instead of trace data.
     */
    UINT32 dbg_mux_bit_set : 3;
    /* dbg_mux_bit_set - Bits[6:4], RW, default = 3'b000 
       Selects which bit to put NTL result on.
     */
    UINT32 rsvd_7 : 13;
    /* rsvd_7 - Bits[19:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ntl_noa_sel : 1;
    /* ntl_noa_sel - Bits[20:20], RW_L, default = 1'b0 
       
       Notes:
       Locked by IODFXLCK
     */
    UINT32 rsvd_21 : 11;
    /* rsvd_21 - Bits[31:21], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MISC_COMMON1_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */














/* CSIPCTRL_0_IIO_DFX_GLOBAL_REG supported on:                                */
/*       IVT_EP (0x40037584)                                                  */
/*       IVT_EX (0x40037584)                                                  */
/*       HSX (0x40037584)                                                     */
/*       BDX (0x40037584)                                                     */
/* Register default value:              0xE0000000                            */
#define CSIPCTRL_0_IIO_DFX_GLOBAL_REG 0x12014584
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x584
 */
typedef union {
  struct {
    UINT32 rsvd : 26;
    /* rsvd - Bits[25:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 vc0_priority : 2;
    /* vc0_priority - Bits[27:26], RW_LB, default = 2'b00  */
    UINT32 vcp_priority : 2;
    /* vcp_priority - Bits[29:28], RW_LB, default = 2'b10  */
    UINT32 vc1_priority : 2;
    /* vc1_priority - Bits[31:30], RW_LB, default = 2'b11  */
  } Bits;
  UINT32 Data;
} CSIPCTRL_0_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
















/* CSIPSUBSAD_IIO_DFX_GLOBAL_REG supported on:                                */
/*       IVT_EP (0x400375A8)                                                  */
/*       IVT_EX (0x400375A8)                                                  */
/*       HSX (0x400375A8)                                                     */
/*       BDX (0x400375A8)                                                     */
/* Register default value:              0x00000000                            */
#define CSIPSUBSAD_IIO_DFX_GLOBAL_REG 0x120145A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x5a8
 */
typedef union {
  struct {
    UINT32 valid : 1;
    /* valid - Bits[0:0], RW, default = 1'b0  */
    UINT32 rsvd_1 : 7;
    /* rsvd_1 - Bits[7:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 legacy_ioh_nodeid5 : 6;
    /* legacy_ioh_nodeid5 - Bits[13:8], RW, default = 6'b000000  */
    UINT32 rsvd_14 : 18;
    /* rsvd_14 - Bits[31:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CSIPSUBSAD_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */






/* SWSW_DBG_MUX_INT_SEL0_IIO_DFX_GLOBAL_REG supported on:                     */
/*       HSX (0x400375D0)                                                     */
/*       BDX (0x400375D0)                                                     */
/* Register default value:              0x00000000                            */
#define SWSW_DBG_MUX_INT_SEL0_IIO_DFX_GLOBAL_REG 0x120145D0
#ifdef HSX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * This register selects which set of iiswsw debug signal sets will be muxed onto 
 * the internal debug bus of the switch. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 6;
    /* dbg_ev_set_ln_sel_0 - Bits[5:0], RWS_L, default = 6'b000000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 6;
    /* dbg_ev_set_ln_sel_1 - Bits[11:6], RWS_L, default = 6'b000000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 6;
    /* dbg_ev_set_ln_sel_2 - Bits[17:12], RWS_L, default = 6'b000000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 6;
    /* dbg_ev_set_ln_sel_3 - Bits[23:18], RWS_L, default = 6'b000000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_4 : 6;
    /* dbg_ev_set_ln_sel_4 - Bits[29:24], RWS_L, default = 6'b000000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} SWSW_DBG_MUX_INT_SEL0_IIO_DFX_GLOBAL_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* HSX_HOST */

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * This register selects which set of iiswsw debug signal sets will be muxed onto 
 * the internal debug bus of the switch. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 7;
    /* dbg_ev_set_ln_sel_0 - Bits[6:0], RWS_L, default = 7'b0000000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 7;
    /* dbg_ev_set_ln_sel_1 - Bits[13:7], RWS_L, default = 7'b0000000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 7;
    /* dbg_ev_set_ln_sel_2 - Bits[20:14], RWS_L, default = 7'b0000000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 7;
    /* dbg_ev_set_ln_sel_3 - Bits[27:21], RWS_L, default = 7'b0000000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} SWSW_DBG_MUX_INT_SEL0_IIO_DFX_GLOBAL_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* BDX_HOST */





/* SWSW_DBG_MUX_INT_SEL2_IIO_DFX_GLOBAL_REG supported on:                     */
/*       BDX (0x400375D8)                                                     */
/* Register default value:              0x00000000                            */
#define SWSW_DBG_MUX_INT_SEL2_IIO_DFX_GLOBAL_REG 0x120145D8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * This register selects which set of iiswsw debug signal sets will be muxed onto 
 * the internal debug bus of the switch. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_8 : 7;
    /* dbg_ev_set_ln_sel_8 - Bits[6:0], RWS_L, default = 7'b0000000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} SWSW_DBG_MUX_INT_SEL2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CC_BIAS_MISC_IIO_DFX_GLOBAL_REG supported on:                              */
/*       IVT_EP (0x40037604)                                                  */
/*       IVT_EX (0x40037604)                                                  */
/*       HSX (0x40037604)                                                     */
/*       BDX (0x40037604)                                                     */
/* Register default value:              0x00000000                            */
#define CC_BIAS_MISC_IIO_DFX_GLOBAL_REG 0x12014604


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x604
 */
typedef union {
  struct {
    UINT32 mb_i_sel : 4;
    /* mb_i_sel - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 rsvd_4 : 12;
    /* rsvd_4 - Bits[15:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tl_iscale : 3;
    /* tl_iscale - Bits[18:16], RWS_L, default = 3'b000  */
    UINT32 rsvd_19 : 13;
    /* rsvd_19 - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_BIAS_MISC_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_BIAS_RX_IIO_DFX_GLOBAL_REG supported on:                                */
/*       IVT_EP (0x40037608)                                                  */
/*       IVT_EX (0x40037608)                                                  */
/*       HSX (0x40037608)                                                     */
/*       BDX (0x40037608)                                                     */
/* Register default value on IVT_EP:    0x08000010                            */
/* Register default value on IVT_EX:    0x08000010                            */
/* Register default value on HSX:       0x08000010                            */
/* Register default value on BDX:       0x05000010                            */
#define CC_BIAS_RX_IIO_DFX_GLOBAL_REG 0x12014608
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x608
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 4;
    /* rsvd_0 - Bits[3:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_ibias_scale : 2;
    /* rx_ibias_scale - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 rsvd_6 : 10;
    /* rsvd_6 - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pi_cml2cmos : 2;
    /* pi_cml2cmos - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 pi_mixdcsc : 2;
    /* pi_mixdcsc - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 pi_idaciscale : 2;
    /* pi_idaciscale - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 pi_iscale : 2;
    /* pi_iscale - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 rx_incm_sel : 6;
    /* rx_incm_sel - Bits[29:24], RWS_L, default = 6'b000101  */
    UINT32 rsvd_30 : 2;
    /* rsvd_30 - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_BIAS_RX_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_BIAS_TX_IIO_DFX_GLOBAL_REG supported on:                                */
/*       IVT_EP (0x4003760C)                                                  */
/*       IVT_EX (0x4003760C)                                                  */
/*       HSX (0x4003760C)                                                     */
/*       BDX (0x4003760C)                                                     */
/* Register default value:              0x0000004B                            */
#define CC_BIAS_TX_IIO_DFX_GLOBAL_REG 0x1201460C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x60c
 */
typedef union {
  struct {
    UINT32 tx_vcm_sel : 5;
    /* tx_vcm_sel - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 rsvd_5 : 1;
    /* rsvd_5 - Bits[5:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tx_vref_rxdetect : 5;
    /* tx_vref_rxdetect - Bits[10:6], RWS_L, default = 5'b00001  */
    UINT32 rsvd_11 : 21;
    /* rsvd_11 - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_BIAS_TX_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_DCC_OVRD_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037610)                                                  */
/*       IVT_EX (0x40037610)                                                  */
/*       HSX (0x40037610)                                                     */
/*       BDX (0x40037610)                                                     */
/* Register default value:              0x00000000                            */
#define CC_DCC_OVRD_IIO_DFX_GLOBAL_REG 0x12014610


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x610
 */
typedef union {
  struct {
    UINT32 txdcc_stopovrden : 1;
    /* txdcc_stopovrden - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 txdcc_stopovrdval : 1;
    /* txdcc_stopovrdval - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 rsvd_2 : 2;
    /* rsvd_2 - Bits[3:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 txdcc_startovrden : 1;
    /* txdcc_startovrden - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 txdcc_startovrdval : 1;
    /* txdcc_startovrdval - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 txdcc_extovrden : 1;
    /* txdcc_extovrden - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 txdcc_extval : 6;
    /* txdcc_extval - Bits[13:8], RWS_L, default = 6'b000000  */
    UINT32 rsvd_14 : 2;
    /* rsvd_14 - Bits[15:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rxdcc_stopovrden : 1;
    /* rxdcc_stopovrden - Bits[16:16], RWS_L, default = 1'b0  */
    UINT32 rxdcc_stopovrdval : 1;
    /* rxdcc_stopovrdval - Bits[17:17], RWS_L, default = 1'b0  */
    UINT32 rsvd_18 : 2;
    /* rsvd_18 - Bits[19:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rxdcc_startovrden : 1;
    /* rxdcc_startovrden - Bits[20:20], RWS_L, default = 1'b0  */
    UINT32 rxdcc_startovrdval : 1;
    /* rxdcc_startovrdval - Bits[21:21], RWS_L, default = 1'b0  */
    UINT32 rsvd_22 : 1;
    /* rsvd_22 - Bits[22:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rxdcc_extovrden : 1;
    /* rxdcc_extovrden - Bits[23:23], RWS_L, default = 1'b0  */
    UINT32 rxdcc_extval : 6;
    /* rxdcc_extval - Bits[29:24], RWS_L, default = 6'b000000  */
    UINT32 rsvd_30 : 2;
    /* rsvd_30 - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_DCC_OVRD_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_DFX_MISC_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037614)                                                  */
/*       IVT_EX (0x40037614)                                                  */
/*       HSX (0x40037614)                                                     */
/*       BDX (0x40037614)                                                     */
/* Register default value:              0x0202C000                            */
#define CC_DFX_MISC_IIO_DFX_GLOBAL_REG 0x12014614
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x614
 */
typedef union {
  struct {
    UINT32 hvm_enable : 1;
    /* hvm_enable - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 burn_in_en : 1;
    /* burn_in_en - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 rsvd_2 : 6;
    /* rsvd_2 - Bits[7:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rterm_hvm_cfg : 6;
    /* rterm_hvm_cfg - Bits[13:8], RWS_L, default = 6'b000000  */
    UINT32 tx_vref_hvm : 5;
    /* tx_vref_hvm - Bits[18:14], RWS_L, default = 5'b01011  */
    UINT32 rsvd_19 : 2;
    /* rsvd_19 - Bits[20:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pi_tst : 3;
    /* pi_tst - Bits[23:21], RWS_L, default = 3'b000  */
    UINT32 dfx_spare : 8;
    /* dfx_spare - Bits[31:24], RWS_L, default = 8'b00000010  */
  } Bits;
  UINT32 Data;
} CC_DFX_MISC_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_DFX_MON0_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037618)                                                  */
/*       IVT_EX (0x40037618)                                                  */
/*       HSX (0x40037618)                                                     */
/*       BDX (0x40037618)                                                     */
/* Register default value on IVT_EP:    0x01000021                            */
/* Register default value on IVT_EX:    0x01000021                            */
/* Register default value on HSX:       0x00000000                            */
/* Register default value on BDX:       0x00000000                            */
#define CC_DFX_MON0_IIO_DFX_GLOBAL_REG 0x12014618


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x618
 */
typedef union {
  struct {
    UINT32 dmon_sel : 7;
    /* dmon_sel - Bits[6:0], RWS_L, default = 7'b0000000  */
    UINT32 dfxp_sel : 6;
    /* dfxp_sel - Bits[12:7], RWS_L, default = 6'b000000  */
    UINT32 dmon2_sel : 7;
    /* dmon2_sel - Bits[19:13], RWS_L, default = 7'b0000000  */
    UINT32 dfxp0_dmon_module_sel : 3;
    /* dfxp0_dmon_module_sel - Bits[22:20], RWS_L, default = 3'b000  */
    UINT32 dfxp1_dmon_module_sel : 3;
    /* dfxp1_dmon_module_sel - Bits[25:23], RWS_L, default = 3'b000  */
    UINT32 dfxp0_dfxp_module_sel : 2;
    /* dfxp0_dfxp_module_sel - Bits[27:26], RWS_L, default = 2'b00  */
    UINT32 dfxp1_dfxp_module_sel : 2;
    /* dfxp1_dfxp_module_sel - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 dfx_lane_sel : 2;
    /* dfx_lane_sel - Bits[31:30], RWS_L, default = 2'b00  */
  } Bits;
  UINT32 Data;
} CC_DFX_MON0_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_DFX_MON1_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x4003761C)                                                  */
/*       IVT_EX (0x4003761C)                                                  */
/*       HSX (0x4003761C)                                                     */
/*       BDX (0x4003761C)                                                     */
/* Register default value:              0x00000000                            */
#define CC_DFX_MON1_IIO_DFX_GLOBAL_REG 0x1201461C


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x61c
 */
typedef union {
  struct {
    UINT32 trace_sel : 6;
    /* trace_sel - Bits[5:0], RWS_L, default = 6'b000000  */
    UINT32 trace_data_module_sel : 2;
    /* trace_data_module_sel - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 eyemon_samplecnt : 4;
    /* eyemon_samplecnt - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 eyemon_mode : 2;
    /* eyemon_mode - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 dfxp0_clkdmon_sel : 2;
    /* dfxp0_clkdmon_sel - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 dfxp1_clkdmon_sel : 2;
    /* dfxp1_clkdmon_sel - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 hsclk_sel : 6;
    /* hsclk_sel - Bits[23:18], RWS_L, default = 6'b000000  */
    UINT32 hsclk2_sel : 6;
    /* hsclk2_sel - Bits[29:24], RWS_L, default = 6'b000000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_DFX_MON1_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_DFX_MON2_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037620)                                                  */
/*       IVT_EX (0x40037620)                                                  */
/*       HSX (0x40037620)                                                     */
/*       BDX (0x40037620)                                                     */
/* Register default value:              0x80000000                            */
#define CC_DFX_MON2_IIO_DFX_GLOBAL_REG 0x12014620


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x620
 */
typedef union {
  struct {
    UINT32 amonv_sel : 6;
    /* amonv_sel - Bits[5:0], RWS_L, default = 6'b000000  */
    UINT32 rsvd_6 : 2;
    /* rsvd_6 - Bits[7:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 amoni_sel : 6;
    /* amoni_sel - Bits[13:8], RWS_L, default = 6'b000000  */
    UINT32 rsvd_14 : 6;
    /* rsvd_14 - Bits[19:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dfxp0_function_sel : 2;
    /* dfxp0_function_sel - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 dfxp1_function_sel : 2;
    /* dfxp1_function_sel - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 amonv_module_sel : 3;
    /* amonv_module_sel - Bits[26:24], RWS_L, default = 3'b000  */
    UINT32 amoni_module_sel : 3;
    /* amoni_module_sel - Bits[29:27], RWS_L, default = 3'b000  */
    UINT32 rsvd_30 : 1;
    /* rsvd_30 - Bits[30:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 amon_puldn_en : 1;
    /* amon_puldn_en - Bits[31:31], RWS_L, default = 1'b1  */
  } Bits;
  UINT32 Data;
} CC_DFX_MON2_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_ICOMP_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037628)                                                  */
/*       IVT_EX (0x40037628)                                                  */
/*       HSX (0x40037628)                                                     */
/*       BDX (0x40037628)                                                     */
/* Register default value:              0x00000002                            */
#define CC_ICOMP_IIO_DFX_GLOBAL_REG 0x12014628
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x628
 */
typedef union {
  struct {
    UINT32 tx_icomp_rc_time : 2;
    /* tx_icomp_rc_time - Bits[1:0], RWS_L, default = 2'b10  */
    UINT32 rsvd_2 : 2;
    /* rsvd_2 - Bits[3:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tx_icomp_gain_sel : 4;
    /* tx_icomp_gain_sel - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 tx_icomp_votes : 2;
    /* tx_icomp_votes - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 rsvd_10 : 22;
    /* rsvd_10 - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_ICOMP_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_RCOMP_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003762C)                                                  */
/*       IVT_EX (0x4003762C)                                                  */
/*       HSX (0x4003762C)                                                     */
/*       BDX (0x4003762C)                                                     */
/* Register default value:              0x00000000                            */
#define CC_RCOMP_IIO_DFX_GLOBAL_REG 0x1201462C


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x62c
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_rt_contcal_en : 1;
    /* rx_rt_contcal_en - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 rsvd_4 : 28;
    /* rsvd_4 - Bits[31:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_RCOMP_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_MISC_CTL_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037630)                                                  */
/*       IVT_EX (0x40037630)                                                  */
/*       HSX (0x40037630)                                                     */
/*       BDX (0x40037630)                                                     */
/* Register default value on IVT_EP:    0x10000000                            */
/* Register default value on IVT_EX:    0x10000000                            */
/* Register default value on HSX:       0x00000000                            */
/* Register default value on BDX:       0x00000000                            */
#define CC_MISC_CTL_IIO_DFX_GLOBAL_REG 0x12014630


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x630
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 8;
    /* rsvd_0 - Bits[7:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tl_rtowen : 1;
    /* tl_rtowen - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 rsvd_9 : 3;
    /* rsvd_9 - Bits[11:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tl_rtval : 4;
    /* tl_rtval - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 rsvd_16 : 16;
    /* rsvd_16 - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_MISC_CTL_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_RX_CTL_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037634)                                                  */
/*       IVT_EX (0x40037634)                                                  */
/*       HSX (0x40037634)                                                     */
/*       BDX (0x40037634)                                                     */
/* Register default value on IVT_EP:    0x00630010                            */
/* Register default value on IVT_EX:    0x00630010                            */
/* Register default value on HSX:       0x00634010                            */
/* Register default value on BDX:       0x00634010                            */
#define CC_RX_CTL_IIO_DFX_GLOBAL_REG 0x12014634


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x634
 */
typedef union {
  struct {
    UINT32 rx_dc_ac : 1;
    /* rx_dc_ac - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 rsvd_1 : 3;
    /* rsvd_1 - Bits[3:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_ckdly_ctl : 2;
    /* rx_ckdly_ctl - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 rsvd_6 : 4;
    /* rsvd_6 - Bits[9:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 sq_en_dc : 1;
    /* sq_en_dc - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 sq_bonus : 1;
    /* sq_bonus - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 sq_onedetect : 1;
    /* sq_onedetect - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 rxsq_ctrl_ac_dc : 3;
    /* rxsq_ctrl_ac_dc - Bits[15:13], RWS_L, default = 3'b010  */
    UINT32 rx_ctle_ctl : 8;
    /* rx_ctle_ctl - Bits[23:16], RWS_L, default = 8'b01100011  */
    UINT32 rsvd_24 : 8;
    /* rsvd_24 - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_RX_CTL_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CC_TX_CTL_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037638)                                                  */
/*       IVT_EX (0x40037638)                                                  */
/*       HSX (0x40037638)                                                     */
/*       BDX (0x40037638)                                                     */
/* Register default value:              0x00000130                            */
#define CC_TX_CTL_IIO_DFX_GLOBAL_REG 0x12014638
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x638
 */
typedef union {
  struct {
    UINT32 tx_rxdet_ctl : 2;
    /* tx_rxdet_ctl - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 rsvd_2 : 2;
    /* rsvd_2 - Bits[3:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 txfifo_depth : 2;
    /* txfifo_depth - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 rsvd_6 : 2;
    /* rsvd_6 - Bits[7:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tx_iqsel : 1;
    /* tx_iqsel - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 rsvd_9 : 3;
    /* rsvd_9 - Bits[11:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dcc_ctl : 3;
    /* dcc_ctl - Bits[14:12], RWS_L, default = 3'b000  */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_TX_CTL_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_PWR_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x4003763C)                                                  */
/*       IVT_EX (0x4003763C)                                                  */
/*       HSX (0x4003763C)                                                     */
/*       BDX (0x4003763C)                                                     */
/* Register default value:              0x00000000                            */
#define CC_PWR_IIO_DFX_GLOBAL_REG 0x1201463C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x63c
 */
typedef union {
  struct {
    UINT32 rx_pwr_cfg : 9;
    /* rx_pwr_cfg - Bits[8:0], RWS_L, default = 9'b000000000  */
    UINT32 rsvd_9 : 7;
    /* rsvd_9 - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tx_pwr_cfg : 6;
    /* tx_pwr_cfg - Bits[21:16], RWS_L, default = 6'b000000  */
    UINT32 rsvd_22 : 9;
    /* rsvd_22 - Bits[30:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pwr_debug_mode : 1;
    /* pwr_debug_mode - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} CC_PWR_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_SPARE_ADDL_IIO_DFX_GLOBAL_REG supported on:                             */
/*       IVT_EP (0x40037640)                                                  */
/*       IVT_EX (0x40037640)                                                  */
/*       HSX (0x40037640)                                                     */
/*       BDX (0x40037640)                                                     */
/* Register default value:              0x00000000                            */
#define CC_SPARE_ADDL_IIO_DFX_GLOBAL_REG 0x12014640
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x640
 */
typedef union {
  struct {
    UINT32 cc_spare_addl_bits : 32;
    /* cc_spare_addl_bits - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CC_SPARE_ADDL_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* CC_MISC_CTL_1_IIO_DFX_GLOBAL_REG supported on:                             */
/*       IVT_EP (0x40037644)                                                  */
/*       IVT_EX (0x40037644)                                                  */
/*       HSX (0x40037644)                                                     */
/*       BDX (0x40037644)                                                     */
/* Register default value on IVT_EP:    0x00360000                            */
/* Register default value on IVT_EX:    0x00360000                            */
/* Register default value on HSX:       0x00360100                            */
/* Register default value on BDX:       0x00360100                            */
#define CC_MISC_CTL_1_IIO_DFX_GLOBAL_REG 0x12014644


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x644
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 8;
    /* rsvd_0 - Bits[7:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 icomp_track_b : 1;
    /* icomp_track_b - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 rsvd_9 : 6;
    /* rsvd_9 - Bits[14:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 blnclegs_ctl_b : 6;
    /* blnclegs_ctl_b - Bits[20:15], RWS_L, default = 6'b101100  */
    UINT32 blnclegs_dis_b : 1;
    /* blnclegs_dis_b - Bits[21:21], RWS_L, default = 1'b1  */
    UINT32 rsvd_22 : 2;
    /* rsvd_22 - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 hvm_mode_b : 8;
    /* hvm_mode_b - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} CC_MISC_CTL_1_IIO_DFX_GLOBAL_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x644
 */
typedef union {
  struct {
    UINT32 txdcc_short_cal : 1;
    /* txdcc_short_cal - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 txdcc_extload_ena : 1;
    /* txdcc_extload_ena - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 txdcc_cal_static : 1;
    /* txdcc_cal_static - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 fwdc_dll_lockdetect_en : 1;
    /* fwdc_dll_lockdetect_en - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 sel_vcm_cml2cmos : 2;
    /* sel_vcm_cml2cmos - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 txdcc_votes : 2;
    /* txdcc_votes - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 icomp_track_b : 1;
    /* icomp_track_b - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 fwdc_canary_capen : 2;
    /* fwdc_canary_capen - Bits[10:9], RWS_L, default = 2'b00  */
    UINT32 rsvd_11 : 4;
    /* rsvd_11 - Bits[14:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 blnclegs_ctl_b : 6;
    /* blnclegs_ctl_b - Bits[20:15], RWS_L, default = 6'b101100  */
    UINT32 blnclegs_dis_b : 1;
    /* blnclegs_dis_b - Bits[21:21], RWS_L, default = 1'b1  */
    UINT32 rsvd_22 : 2;
    /* rsvd_22 - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 hvm_mode_b : 8;
    /* hvm_mode_b - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} CC_MISC_CTL_1_IIO_DFX_GLOBAL_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* CC_MISC_CTL_2_IIO_DFX_GLOBAL_REG supported on:                             */
/*       IVT_EP (0x40037648)                                                  */
/*       IVT_EX (0x40037648)                                                  */
/*       HSX (0x40037648)                                                     */
/*       BDX (0x40037648)                                                     */
/* Register default value:              0x00000200                            */
#define CC_MISC_CTL_2_IIO_DFX_GLOBAL_REG 0x12014648


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x648
 */
typedef union {
  struct {
    UINT32 tx_cascdisable : 1;
    /* tx_cascdisable - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 rsvd_1 : 7;
    /* rsvd_1 - Bits[7:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rt_onehot : 1;
    /* rt_onehot - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 rxincmgen_pulldn : 2;
    /* rxincmgen_pulldn - Bits[10:9], RWS_L, default = 2'b01  */
    UINT32 rsvd_11 : 3;
    /* rsvd_11 - Bits[13:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pcie_ovp_en : 1;
    /* pcie_ovp_en - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 rx_rterm_ovp_en : 1;
    /* rx_rterm_ovp_en - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd_16 : 16;
    /* rsvd_16 - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_MISC_CTL_2_IIO_DFX_GLOBAL_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x648
 */
typedef union {
  struct {
    UINT32 tx_cascdisable : 1;
    /* tx_cascdisable - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 rsvd_1 : 7;
    /* rsvd_1 - Bits[7:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rt_onehot : 1;
    /* rt_onehot - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 rxincmgen_pulldn : 2;
    /* rxincmgen_pulldn - Bits[10:9], RWS_L, default = 2'b01  */
    UINT32 rsvd_11 : 3;
    /* rsvd_11 - Bits[13:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pcie_ovp_en : 1;
    /* pcie_ovp_en - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 rx_rterm_ovp_en : 1;
    /* rx_rterm_ovp_en - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 txdcc_extload_val_bin : 5;
    /* txdcc_extload_val_bin - Bits[20:16], RWS_L, default = 5'b00000  */
    UINT32 txdcc_extload_val_therm : 5;
    /* txdcc_extload_val_therm - Bits[25:21], RWS_L, default = 5'b00000  */
    UINT32 txdcc_gain_sel : 3;
    /* txdcc_gain_sel - Bits[28:26], RWS_L, default = 3'b000  */
    UINT32 rsvd_29 : 3;
    /* rsvd_29 - Bits[31:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_MISC_CTL_2_IIO_DFX_GLOBAL_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* CC_SPARE2_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       HSX (0x4003764C)                                                     */
/*       BDX (0x4003764C)                                                     */
/* Register default value:              0x00000000                            */
#define CC_SPARE2_IIO_DFX_GLOBAL_REG 0x1201464C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x64c
 */
typedef union {
  struct {
    UINT32 cc_spare2 : 16;
    /* cc_spare2 - Bits[15:0], RWS_L, default = 16'b0000000000000000  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_SPARE2_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CC_SPARE_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037650)                                                  */
/*       IVT_EX (0x40037650)                                                  */
/*       HSX (0x40037650)                                                     */
/*       BDX (0x40037650)                                                     */
/* Register default value:              0x0000000C                            */
#define CC_SPARE_IIO_DFX_GLOBAL_REG 0x12014650
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x650
 */
typedef union {
  struct {
    UINT32 cc_spare : 16;
    /* cc_spare - Bits[15:0], RWS_L, default = 16'b0000000000001100  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CC_SPARE_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* UNIPHY_FUSE_CTRL_IIO_DFX_GLOBAL_REG supported on:                          */
/*       IVT_EP (0x10037654)                                                  */
/*       IVT_EX (0x10037654)                                                  */
/*       HSX (0x10037654)                                                     */
/*       BDX (0x10037654)                                                     */
/* Register default value:              0x00                                  */
#define UNIPHY_FUSE_CTRL_IIO_DFX_GLOBAL_REG 0x12011654
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x654
 */
typedef union {
  struct {
    UINT8 csr_override : 1;
    /* csr_override - Bits[0:0], RWS_L, default = 1'b0  */
    UINT8 rsvd : 7;
    /* rsvd - Bits[7:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT8 Data;
} UNIPHY_FUSE_CTRL_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */






/* DFX_NTL_CTL_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037660)                                                  */
/*       IVT_EX (0x40037660)                                                  */
/*       HSX (0x40037660)                                                     */
/*       BDX (0x40037660)                                                     */
/* Register default value:              0x00000000                            */
#define DFX_NTL_CTL_IIO_DFX_GLOBAL_REG 0x12014660
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x660
 */
typedef union {
  struct {
    UINT32 rx_pullhi_n_even : 1;
    /* rx_pullhi_n_even - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 rx_pullhi_n_odd : 1;
    /* rx_pullhi_n_odd - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 rx_pullhi_p_even : 1;
    /* rx_pullhi_p_even - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 rx_pullhi_p_odd : 1;
    /* rx_pullhi_p_odd - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 tx_pullhi_n_even : 1;
    /* tx_pullhi_n_even - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 tx_pullhi_n_odd : 1;
    /* tx_pullhi_n_odd - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 tx_pullhi_p_even : 1;
    /* tx_pullhi_p_even - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 tx_pullhi_p_odd : 1;
    /* tx_pullhi_p_odd - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 ntl_capt_mode : 2;
    /* ntl_capt_mode - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 rsvd_10 : 2;
    /* rsvd_10 - Bits[11:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ntl_comp_all : 1;
    /* ntl_comp_all - Bits[12:12], RO_V, default = 1'b0  */
    UINT32 rsvd_13 : 3;
    /* rsvd_13 - Bits[15:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ntl_ovrd_rx_pullhi_n_val : 2;
    /* ntl_ovrd_rx_pullhi_n_val - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 ntl_ovrd_rx_pullhi_p_val : 2;
    /* ntl_ovrd_rx_pullhi_p_val - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 ntl_ovrd_tx_pullhi_n_val : 2;
    /* ntl_ovrd_tx_pullhi_n_val - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 ntl_ovrd_tx_pullhi_p_val : 2;
    /* ntl_ovrd_tx_pullhi_p_val - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 rsvd_24 : 8;
    /* rsvd_24 - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFX_NTL_CTL_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */




/* IIO_DFX_L1_CLK_GATING_REG_IIO_DFX_GLOBAL_REG supported on:                 */
/*       IVT_EP (0x40037668)                                                  */
/*       IVT_EX (0x40037668)                                                  */
/*       HSX (0x40037668)                                                     */
/*       BDX (0x40037668)                                                     */
/* Register default value:              0x00000000                            */
#define IIO_DFX_L1_CLK_GATING_REG_IIO_DFX_GLOBAL_REG 0x12014668
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x668
 */
typedef union {
  struct {
    UINT32 blkl1_exit_en : 1;
    /* blkl1_exit_en - Bits[0:0], RW, default = 1'b0  */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIO_DFX_L1_CLK_GATING_REG_IIO_DFX_GLOBAL_STRUCT;
#endif /* ASM_INC */


/* TSWCTL_N_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037670)                                                  */
/*       IVT_EX (0x40037670)                                                  */
/*       HSX (0x40037670)                                                     */
/*       BDX (0x40037670)                                                     */
/* Register default value on IVT_EP:    0x00000200                            */
/* Register default value on IVT_EX:    0x00000200                            */
/* Register default value on HSX:       0x0000020F                            */
/* Register default value on BDX:       0x0000020F                            */
#define TSWCTL_N_IIO_DFX_GLOBAL_REG 0x12014670


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x670
 */
typedef union {
  struct {
    UINT32 enable_irp_intlv_iou2 : 2;
    /* enable_irp_intlv_iou2 - Bits[1:0], RW_L, default = 2'b11 
       
       "00" : P and NP -> IRP0
       "01" : P -> IRP0 and NP -> IRP1
       "10" : P -> IRP1 and NP -> IRP0
       "11" : Interleave (addr[6]='0' -> IRP0 and addr[6]='1' -> IRP1)
       
       Overridden when swdbgctl0.enable_irp_intlv==0 (all traffic to IRP0).
       
       Locked by RSPLCK
     */
    UINT32 enable_irp_intlv_cbdma : 2;
    /* enable_irp_intlv_cbdma - Bits[3:2], RW_L, default = 2'b11 
       
       "00" : P and NP -> IRP1
       "01" : P -> IRP0 and NP -> IRP1
       "10" : P -> IRP1 and NP -> IRP0
       "11" : Interleave (addr[6]='0' -> IRP0 and addr[6]='1' -> IRP1)
       
       Overridden when swdbgctl0.enable_irp_intlv==0 (all traffic to IRP0).
       
       Locked by RSPLCK
     */
    UINT32 rsvd : 1;
    /* rsvd - Bits[4:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 csr_dfx_disable_lt_pcie_fix : 1;
    /* csr_dfx_disable_lt_pcie_fix - Bits[5:5], RW_L, default = 1'b0  */
    UINT32 csr_dis_vcp_p2p_ma_fix : 1;
    /* csr_dis_vcp_p2p_ma_fix - Bits[6:6], RW_L, default = 1'b0  */
    UINT32 csr_en_vc1_ma : 1;
    /* csr_en_vc1_ma - Bits[7:7], RW_L, default = 1'b0  */
    UINT32 csr_en_ds_lt_in_vira : 1;
    /* csr_en_ds_lt_in_vira - Bits[8:8], RW_L, default = 1'b0 
       Enable outbound address from processing downstream lt transactions during vira
       Locked by RSPLCK
     */
    UINT32 csr_en_ds_msg_in_vira : 1;
    /* csr_en_ds_msg_in_vira - Bits[9:9], RW_L, default = 1'b1 
       Enable outbound address from processing downstream msg transactions during vira
       Locked by RSPLCK
     */
    UINT32 csr_en_ds_cfg_in_vira : 1;
    /* csr_en_ds_cfg_in_vira - Bits[10:10], RW_L, default = 1'b0 
       Enable outbound address from processing downstream cfg transactions during vira
       Locked by RSPLCK
     */
    UINT32 cfg_mabt_hint_disable : 1;
    /* cfg_mabt_hint_disable - Bits[11:11], RW_L, default = 1'b0 
       Disable outbound address from processing MABT Hint for downstream config 
       transactions initiated from coherent interface. 
       Locked by RSPLCK
     */
    UINT32 lt_mabt_hint_disable : 1;
    /* lt_mabt_hint_disable - Bits[12:12], RW_L, default = 1'b0 
       Disable CSI FIFO controller from propagating the MABT_HINT for LT transactions.
       Locked by RSPLCK
     */
    UINT32 lt_mabt_errlog_enable : 1;
    /* lt_mabt_errlog_enable - Bits[13:13], RW_L, default = 1'b0 
       Enable error logging for LT cycles that were MABT'ed
       Locked by RSPLCK
     */
    UINT32 csr_dis_vt_completion_viral_fix : 1;
    /* csr_dis_vt_completion_viral_fix - Bits[14:14], RW_L, default = 1'b0  */
    UINT32 csr_disable_bar_access_in_viral : 1;
    /* csr_disable_bar_access_in_viral - Bits[15:15], RW_L, default = 1'b0 
       Disable MMIO access during viral
       Locked by RSPLCK
     */
    UINT32 csr_dis_cb_completion_fix : 1;
    /* csr_dis_cb_completion_fix - Bits[16:16], RW_L, default = 1'b0 
       Disable 4540829 fix for CB completion
       Locked by RSPLCK
     */
    UINT32 enable_cb_iou2_cpl_intlv : 1;
    /* enable_cb_iou2_cpl_intlv - Bits[17:17], RW_L, default = 1'b0 
       '1' : Enable performance mode that where CBDMA and IOU2 completions to 
       interleave 
       between using the two outbound datapaths.
       '0' : Disable performance mode that where CBDMA and IOU2 completions to 
       interleave 
       between using the two outbound datapaths.
       
       Note: This CSR should be set to '1' in conjuction with tswctl_n[3:0] that steers
       CBDMA and IOU2 inbound traffic uni-directional to a given IRP side. If CBDMA
       and IOU2 inbound traffic is allowed to interleave between IRP sides, this CSR
       should be disabled to '0'.
       
       Locked by RSPLCK
     */
    UINT32 link_upok_skip_ro_empty : 1;
    /* link_upok_skip_ro_empty - Bits[18:18], RW_L, default = 1'b0 
       Skip waiting for the RO block to signal empty before resetting switch pointers 
       on surprise link down. Defeature bit for HSX HSD 4620429. 
     */
    UINT32 irp_mabt_hint_disable : 1;
    /* irp_mabt_hint_disable - Bits[19:19], RW_L, default = 1'b0 
       Ignore the master abort hint from IRP on outbound requests.
     */
    UINT32 spare : 12;
    /* spare - Bits[31:20], RW_L, default = 12'b000000000000  */
  } Bits;
  UINT32 Data;
} TSWCTL_N_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* TSWCTL_W_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037674)                                                  */
/*       IVT_EX (0x40037674)                                                  */
/*       HSX (0x40037674)                                                     */
/*       BDX (0x40037674)                                                     */
/* Register default value on IVT_EP:    0x00000000                            */
/* Register default value on IVT_EX:    0x00000000                            */
/* Register default value on HSX:       0x00000001                            */
/* Register default value on BDX:       0x00000001                            */
#define TSWCTL_W_IIO_DFX_GLOBAL_REG 0x12014674


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x674
 */
typedef union {
  struct {
    UINT32 en_tph_with_ro : 1;
    /* en_tph_with_ro - Bits[0:0], RW_L, default = 1'b1 
       Enable TPH hints to propagate for RO=1 writes.
     */
    UINT32 force_no_snp_on_vc1_vcm : 1;
    /* force_no_snp_on_vc1_vcm - Bits[1:1], RW_L, default = 1'b0 
       Force VC1 and VCm traffic to be nonsnoop.
     */
    UINT32 csr_dbg_tswctl_w : 30;
    /* csr_dbg_tswctl_w - Bits[31:2], RW_L, default = 30'b000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} TSWCTL_W_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* TSWCTL_E_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037678)                                                  */
/*       IVT_EX (0x40037678)                                                  */
/*       HSX (0x40037678)                                                     */
/*       BDX (0x40037678)                                                     */
/* Register default value:              0x00000001                            */
#define TSWCTL_E_IIO_DFX_GLOBAL_REG 0x12014678


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.7.CFG.xml.
 * generated by critter 06_7_0x678
 */
typedef union {
  struct {
    UINT32 csr_jkt_enable_vtdcorruption_fix : 1;
    /* csr_jkt_enable_vtdcorruption_fix - Bits[0:0], RW_L, default = 1'b1 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 csr_dfx_disable_iou01_parity_fix : 1;
    /* csr_dfx_disable_iou01_parity_fix - Bits[1:1], RW_L, default = 1'b0  */
    UINT32 csr_dfx_disable_iou2_parity_fix : 1;
    /* csr_dfx_disable_iou2_parity_fix - Bits[2:2], RW_L, default = 1'b0  */
    UINT32 csr_dfx_disable_parity_fix : 1;
    /* csr_dfx_disable_parity_fix - Bits[3:3], RW_L, default = 1'b0  */
    UINT32 csr_dfx_disable_fail_link_ma : 1;
    /* csr_dfx_disable_fail_link_ma - Bits[4:4], RW_L, default = 1'b0  */
    UINT32 csr_dfx_disable_outbound_parity_fix : 1;
    /* csr_dfx_disable_outbound_parity_fix - Bits[5:5], RW_L, default = 1'b0  */
    UINT32 dis_msgblk_ob_fc_split : 1;
    /* dis_msgblk_ob_fc_split - Bits[6:6], RW_L, default = 1'b0  */
    UINT32 csr_dbg_tswctl_e : 25;
    /* csr_dbg_tswctl_e - Bits[31:7], RW_L, default = 25'b0000000000000000000000000  */
  } Bits;
  UINT32 Data;
} TSWCTL_E_IIO_DFX_GLOBAL_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */












































/* IIMI_DBGBUSCNTRL0_IIO_DFX_GLOBAL_REG supported on:                         */
/*       IVT_EP (0x40037110)                                                  */
/*       IVT_EX (0x40037110)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSCNTRL0_IIO_DFX_GLOBAL_REG 0x12014110



/* IIMI_DBGBUSCNTRL1_IIO_DFX_GLOBAL_REG supported on:                         */
/*       IVT_EP (0x20037114)                                                  */
/*       IVT_EX (0x20037114)                                                  */
/* Register default value:              0x0001                                */
#define IIMI_DBGBUSCNTRL1_IIO_DFX_GLOBAL_REG 0x12012114



/* IIMI_DBGBUSCNTRL2_IIO_DFX_GLOBAL_REG supported on:                         */
/*       IVT_EP (0x20037118)                                                  */
/*       IVT_EX (0x20037118)                                                  */
/* Register default value:              0x0000                                */
#define IIMI_DBGBUSCNTRL2_IIO_DFX_GLOBAL_REG 0x12012118



/* IIMI_DBGBUSCNTRL3_IIO_DFX_GLOBAL_REG supported on:                         */
/*       IVT_EP (0x40037138)                                                  */
/*       IVT_EX (0x40037138)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSCNTRL3_IIO_DFX_GLOBAL_REG 0x12014138



/* IIMI_DBGBUSCNTRL4_IIO_DFX_GLOBAL_REG supported on:                         */
/*       IVT_EP (0x2003713C)                                                  */
/*       IVT_EX (0x2003713C)                                                  */
/* Register default value:              0x0000                                */
#define IIMI_DBGBUSCNTRL4_IIO_DFX_GLOBAL_REG 0x1201213C



/* IIMI_DBGBUSMATCHLOW_IIO_DFX_GLOBAL_REG supported on:                       */
/*       IVT_EP (0x4003718C)                                                  */
/*       IVT_EX (0x4003718C)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSMATCHLOW_IIO_DFX_GLOBAL_REG 0x1201418C



/* IIMI_DBGBUSMATCHMID_IIO_DFX_GLOBAL_REG supported on:                       */
/*       IVT_EP (0x40037190)                                                  */
/*       IVT_EX (0x40037190)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSMATCHMID_IIO_DFX_GLOBAL_REG 0x12014190



/* IIMI_DBGBUSMATCHHIGH_IIO_DFX_GLOBAL_REG supported on:                      */
/*       IVT_EP (0x10037194)                                                  */
/*       IVT_EX (0x10037194)                                                  */
/* Register default value:              0x00                                  */
#define IIMI_DBGBUSMATCHHIGH_IIO_DFX_GLOBAL_REG 0x12011194



/* IIMI_DBGBUSMASKLOW_IIO_DFX_GLOBAL_REG supported on:                        */
/*       IVT_EP (0x40037198)                                                  */
/*       IVT_EX (0x40037198)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSMASKLOW_IIO_DFX_GLOBAL_REG 0x12014198



/* IIMI_DBGBUSMASKMID_IIO_DFX_GLOBAL_REG supported on:                        */
/*       IVT_EP (0x4003719C)                                                  */
/*       IVT_EX (0x4003719C)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_DBGBUSMASKMID_IIO_DFX_GLOBAL_REG 0x1201419C



/* IIMI_DBGBUSMASKHIGH_IIO_DFX_GLOBAL_REG supported on:                       */
/*       IVT_EP (0x100371A0)                                                  */
/*       IVT_EX (0x100371A0)                                                  */
/* Register default value:              0x00                                  */
#define IIMI_DBGBUSMASKHIGH_IIO_DFX_GLOBAL_REG 0x120111A0



/* IIMI_ASC0LDVAL_IIO_DFX_GLOBAL_REG supported on:                            */
/*       IVT_EP (0x400371B0)                                                  */
/*       IVT_EX (0x400371B0)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_ASC0LDVAL_IIO_DFX_GLOBAL_REG 0x120141B0



/* IIMI_ASC1LDVAL_IIO_DFX_GLOBAL_REG supported on:                            */
/*       IVT_EP (0x400371B4)                                                  */
/*       IVT_EX (0x400371B4)                                                  */
/* Register default value:              0x00000000                            */
#define IIMI_ASC1LDVAL_IIO_DFX_GLOBAL_REG 0x120141B4



/* MIRNG_IIO_DFX_GLOBAL_REG supported on:                                     */
/*       IVT_EP (0x40037200)                                                  */
/*       IVT_EX (0x40037200)                                                  */
/* Register default value:              0x180000C0                            */
#define MIRNG_IIO_DFX_GLOBAL_REG 0x12014200



/* MIDELS_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x40037204)                                                  */
/*       IVT_EX (0x40037204)                                                  */
/* Register default value:              0x00000000                            */
#define MIDELS_IIO_DFX_GLOBAL_REG 0x12014204



/* MIPDELS1_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003720C)                                                  */
/*       IVT_EX (0x4003720C)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS1_IIO_DFX_GLOBAL_REG 0x1201420C



/* MIPDELS3_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037214)                                                  */
/*       IVT_EX (0x40037214)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS3_IIO_DFX_GLOBAL_REG 0x12014214



/* MIPDELS5_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003721C)                                                  */
/*       IVT_EX (0x4003721C)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS5_IIO_DFX_GLOBAL_REG 0x1201421C



/* MIPDELS6_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037220)                                                  */
/*       IVT_EX (0x40037220)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS6_IIO_DFX_GLOBAL_REG 0x12014220



/* MIPDELS7_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037224)                                                  */
/*       IVT_EX (0x40037224)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS7_IIO_DFX_GLOBAL_REG 0x12014224



/* MIPDELS8_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037228)                                                  */
/*       IVT_EX (0x40037228)                                                  */
/* Register default value:              0x00000000                            */
#define MIPDELS8_IIO_DFX_GLOBAL_REG 0x12014228



/* IIONOASEL_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x4003722C)                                                  */
/*       IVT_EX (0x4003722C)                                                  */
/* Register default value:              0x00F00000                            */
#define IIONOASEL_IIO_DFX_GLOBAL_REG 0x1201422C



/* TSWRNG_IIO_DFX_GLOBAL_REG supported on:                                    */
/*       IVT_EP (0x40037300)                                                  */
/*       IVT_EX (0x40037300)                                                  */
/* Register default value:              0x180000C0                            */
#define TSWRNG_IIO_DFX_GLOBAL_REG 0x12014300



/* TSWDELS0_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037304)                                                  */
/*       IVT_EX (0x40037304)                                                  */
/* Register default value:              0x00000000                            */
#define TSWDELS0_IIO_DFX_GLOBAL_REG 0x12014304



/* TSWRNG_EAST_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037310)                                                  */
/*       IVT_EX (0x40037310)                                                  */
/* Register default value:              0x180000C0                            */
#define TSWRNG_EAST_IIO_DFX_GLOBAL_REG 0x12014310



/* TSWDELS0_EAST_IIO_DFX_GLOBAL_REG supported on:                             */
/*       IVT_EP (0x40037314)                                                  */
/*       IVT_EX (0x40037314)                                                  */
/* Register default value:              0x00000000                            */
#define TSWDELS0_EAST_IIO_DFX_GLOBAL_REG 0x12014314



/* DBG_MUX47_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x4003739C)                                                  */
/*       IVT_EX (0x4003739C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX47_IIO_DFX_GLOBAL_REG 0x1201439C



/* DBG_MUX48_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373A0)                                                  */
/*       IVT_EX (0x400373A0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX48_IIO_DFX_GLOBAL_REG 0x120143A0



/* DBG_MUX50_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373A8)                                                  */
/*       IVT_EX (0x400373A8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX50_IIO_DFX_GLOBAL_REG 0x120143A8



/* DBG_MUX51_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373AC)                                                  */
/*       IVT_EX (0x400373AC)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX51_IIO_DFX_GLOBAL_REG 0x120143AC



/* DBG_MUX52_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373B0)                                                  */
/*       IVT_EX (0x400373B0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX52_IIO_DFX_GLOBAL_REG 0x120143B0



/* DBG_MUX53_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373B4)                                                  */
/*       IVT_EX (0x400373B4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX53_IIO_DFX_GLOBAL_REG 0x120143B4



/* DBG_MUX54_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373D0)                                                  */
/*       IVT_EX (0x400373D0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX54_IIO_DFX_GLOBAL_REG 0x120143D0



/* DBG_MUX55_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400373D4)                                                  */
/*       IVT_EX (0x400373D4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX55_IIO_DFX_GLOBAL_REG 0x120143D4



/* DBG_MUX0_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003744C)                                                  */
/*       IVT_EX (0x4003744C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX0_IIO_DFX_GLOBAL_REG 0x1201444C



/* DBG_MUX1_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037450)                                                  */
/*       IVT_EX (0x40037450)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX1_IIO_DFX_GLOBAL_REG 0x12014450



/* DBG_MUX2_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037454)                                                  */
/*       IVT_EX (0x40037454)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX2_IIO_DFX_GLOBAL_REG 0x12014454



/* DBG_MUX3_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037458)                                                  */
/*       IVT_EX (0x40037458)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX3_IIO_DFX_GLOBAL_REG 0x12014458



/* DBG_MUX4_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003745C)                                                  */
/*       IVT_EX (0x4003745C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX4_IIO_DFX_GLOBAL_REG 0x1201445C



/* DBG_MUX5_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037460)                                                  */
/*       IVT_EX (0x40037460)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX5_IIO_DFX_GLOBAL_REG 0x12014460



/* DBG_MUX6_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037464)                                                  */
/*       IVT_EX (0x40037464)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX6_IIO_DFX_GLOBAL_REG 0x12014464



/* DBG_MUX7_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037468)                                                  */
/*       IVT_EX (0x40037468)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX7_IIO_DFX_GLOBAL_REG 0x12014468



/* DBG_MUX8_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x4003746C)                                                  */
/*       IVT_EX (0x4003746C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX8_IIO_DFX_GLOBAL_REG 0x1201446C



/* DBG_MUX9_IIO_DFX_GLOBAL_REG supported on:                                  */
/*       IVT_EP (0x40037470)                                                  */
/*       IVT_EX (0x40037470)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX9_IIO_DFX_GLOBAL_REG 0x12014470



/* DBG_MUX10_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037474)                                                  */
/*       IVT_EX (0x40037474)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX10_IIO_DFX_GLOBAL_REG 0x12014474



/* DBG_MUX11_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037478)                                                  */
/*       IVT_EX (0x40037478)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX11_IIO_DFX_GLOBAL_REG 0x12014478



/* DBG_MUX12_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x4003747C)                                                  */
/*       IVT_EX (0x4003747C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX12_IIO_DFX_GLOBAL_REG 0x1201447C



/* DBG_MUX19_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x40037498)                                                  */
/*       IVT_EX (0x40037498)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX19_IIO_DFX_GLOBAL_REG 0x12014498



/* DBG_MUX20_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x4003749C)                                                  */
/*       IVT_EX (0x4003749C)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX20_IIO_DFX_GLOBAL_REG 0x1201449C



/* DBG_MUX29_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374C0)                                                  */
/*       IVT_EX (0x400374C0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX29_IIO_DFX_GLOBAL_REG 0x120144C0



/* DBG_MUX30_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374C4)                                                  */
/*       IVT_EX (0x400374C4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX30_IIO_DFX_GLOBAL_REG 0x120144C4



/* DBG_MUX31_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374C8)                                                  */
/*       IVT_EX (0x400374C8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX31_IIO_DFX_GLOBAL_REG 0x120144C8



/* DBG_MUX32_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374D0)                                                  */
/*       IVT_EX (0x400374D0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX32_IIO_DFX_GLOBAL_REG 0x120144D0



/* DBG_MUX33_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374D4)                                                  */
/*       IVT_EX (0x400374D4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX33_IIO_DFX_GLOBAL_REG 0x120144D4



/* DBG_MUX34_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374D8)                                                  */
/*       IVT_EX (0x400374D8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX34_IIO_DFX_GLOBAL_REG 0x120144D8



/* DBG_MUX35_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374DC)                                                  */
/*       IVT_EX (0x400374DC)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX35_IIO_DFX_GLOBAL_REG 0x120144DC



/* DBG_MUX36_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374E0)                                                  */
/*       IVT_EX (0x400374E0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX36_IIO_DFX_GLOBAL_REG 0x120144E0



/* DBG_MUX37_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374E4)                                                  */
/*       IVT_EX (0x400374E4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX37_IIO_DFX_GLOBAL_REG 0x120144E4



/* DBG_MUX41_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374F4)                                                  */
/*       IVT_EX (0x400374F4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX41_IIO_DFX_GLOBAL_REG 0x120144F4



/* DBG_MUX42_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374F8)                                                  */
/*       IVT_EX (0x400374F8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX42_IIO_DFX_GLOBAL_REG 0x120144F8



/* DBG_MUX43_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400374FC)                                                  */
/*       IVT_EX (0x400374FC)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX43_IIO_DFX_GLOBAL_REG 0x120144FC



/* DBG_MUX56_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375C0)                                                  */
/*       IVT_EX (0x400375C0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX56_IIO_DFX_GLOBAL_REG 0x120145C0



/* DBG_MUX57_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375C4)                                                  */
/*       IVT_EX (0x400375C4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX57_IIO_DFX_GLOBAL_REG 0x120145C4



/* DBG_MUX58_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375C8)                                                  */
/*       IVT_EX (0x400375C8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX58_IIO_DFX_GLOBAL_REG 0x120145C8



/* DBG_MUX59_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375CC)                                                  */
/*       IVT_EX (0x400375CC)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX59_IIO_DFX_GLOBAL_REG 0x120145CC



/* DBG_MUX60_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375D0)                                                  */
/*       IVT_EX (0x400375D0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX60_IIO_DFX_GLOBAL_REG 0x120145D0



/* DBG_MUX61_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375D4)                                                  */
/*       IVT_EX (0x400375D4)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX61_IIO_DFX_GLOBAL_REG 0x120145D4



/* DBG_MUX62_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375D8)                                                  */
/*       IVT_EX (0x400375D8)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX62_IIO_DFX_GLOBAL_REG 0x120145D8



/* DBG_MUX63_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375DC)                                                  */
/*       IVT_EX (0x400375DC)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX63_IIO_DFX_GLOBAL_REG 0x120145DC



/* DBG_MUX64_IIO_DFX_GLOBAL_REG supported on:                                 */
/*       IVT_EP (0x400375E0)                                                  */
/*       IVT_EX (0x400375E0)                                                  */
/* Register default value:              0x00000000                            */
#define DBG_MUX64_IIO_DFX_GLOBAL_REG 0x120145E0



/* DBG_MUX_CTRL_SO_IIO_DFX_GLOBAL_REG supported on:                           */
/*       IVT_EP (0x100375EF)                                                  */
/*       IVT_EX (0x100375EF)                                                  */
/* Register default value:              0x00                                  */
#define DBG_MUX_CTRL_SO_IIO_DFX_GLOBAL_REG 0x120115EF



/* CC_BANDGAP_IIO_DFX_GLOBAL_REG supported on:                                */
/*       IVT_EP (0x40037600)                                                  */
/*       IVT_EX (0x40037600)                                                  */
/* Register default value:              0x00000000                            */
#define CC_BANDGAP_IIO_DFX_GLOBAL_REG 0x12014600



/* CC_COMP_STS_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x40037624)                                                  */
/*       IVT_EX (0x40037624)                                                  */
/* Register default value:              0x00000000                            */
#define CC_COMP_STS_IIO_DFX_GLOBAL_REG 0x12014624



/* CC_PLL_MISC_IIO_DFX_GLOBAL_REG supported on:                               */
/*       IVT_EP (0x4003764C)                                                  */
/*       IVT_EX (0x4003764C)                                                  */
/* Register default value:              0x00000000                            */
#define CC_PLL_MISC_IIO_DFX_GLOBAL_REG 0x1201464C



/* DFX_BNDRY_SCAN_IIO_DFX_GLOBAL_REG supported on:                            */
/*       IVT_EP (0x10037664)                                                  */
/*       IVT_EX (0x10037664)                                                  */
/* Register default value:              0x12                                  */
#define DFX_BNDRY_SCAN_IIO_DFX_GLOBAL_REG 0x12011664



#endif /* IIO_DFX_GLOBAL_h */
